EP7212 Datasheet, PDF (108/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
EXPCLK
DRA[12:0]
RAS[3:0]
CAS[3:0]
Held
t_CSA
t_RAS ^tRC
Row
Col
D[31:0]
Held
NMOE
NMWE
Figure 22. DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz
NOTES:
1). t_CSA (CAS set-up time) = 15 ns max at 18.432 MHz and 20 ns at 13 MHz
2) t_RAS (RAS pulse width) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz
3) t_RC (cycle time) = 180 ns max at 18.432 MHz and 230 ns at 13 MHz
4) The filled-in grey area is a don’t care.
When DRAMs are placed in self-refresh (entering the Standby State), the same timings, except that t_RAS
is extended indefinitely.
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DS474PP1