EP7212 Datasheet, PDF (47/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
an 80 Hz refresh rate is approximately
6.2 Mbytes/sec. Assuming the frame buffer is
stored in a 32-bit wide the maximum theoretical
bandwidth available is 86 Mbytes/sec at
36.864 MHz, or 29.7 Mbytes/sec at 13 MHz.
The LCD controller uses a nine stage 32-bit wide
FIFO to buffer display data. The LCD controller re-
quests new data when there are five words remain-
ing in the FIFO. This means that for a ½ VGA
display at 4 bits-per-pixel and 80 Hz refresh rate,
the maximum allowable DMA latency is approxi-
mately 3.25 µsec ((5 words x 8 bits/byte) / (640 x
240 x 4bpp x 80 Hz)) = 3.25 µsec). The worst-case
latency is the total number of cycles from when the
DMA request appears to when the first DMA data
word actually becomes available at the FIFO.
DMA has the highest priority, so it will always hap-
pen next in the system. The maximum number of
cycles required is 36 from the point at which the
DMA request occurs to the point at which the STM
is complete, then another 6 cycles before the data
actually arrives at the FIFO from the first DMA
read. This creates a total of 42 cycles. Assuming
the frame buffer is located in 32-bit wide, the
worst-case latency is almost exactly 3.2 µs, with
13 MHz page mode cycles. With each cycle con-
suming ~77 ns (i.e., 1/1 MHz), the value of 3.2 µs
comes from 42 cycles x 77 ns/cycle = ~3.23 µsec.
If 16-bit wide, then the worst-case latency will dou-
ble. In this case, the maximum permissible display
size will be halved, to approximately 320 x 240 pix-
els, assuming the same pixel depth and refresh rate
has to be maintained. If the frame buffer is to be
stored in static memory, then further calculations
must be performed. If 18 MHz mode is selected,
and 32-bit wide, then the worst-case latency will be
2.26 µsec (i.e., 42 cycles x 54 nsec/cycle). If
36 MHz mode is selected, and 32-bit wide, then the
worst-case latency drops down to 1.49 µs. This cal-
culation is a little more complex for 36 MHz mode
of operation. The total number of cycles = (12 x 4)
+ 7 = 55. Thus, 55 x 27 ns = ~1.49 µsec.
Figure 11 shows the organization of the video map
for all combinations of bits-per-pixel.
The refresh rate is not affected by the number of
bits-per-pixel; however the LCD controller fetches
twice the data per refresh for 4 bits-per-pixel com-
pared to 2 bits-per-pixel. The main reason for re-
ducing the number of bits-per-pixel is to reduce the
power consumption of the memory where the video
frame buffer is mapped.
3.15 Timer Counters
Two identical timer counters are integrated into the
EP7212. These are referred to as TC1 and TC2.
Each timer counter has an associated 16-bit read /
write data register and some control bits in the sys-
tem control register. Each counter is loaded with
the value written to the data register immediately.
This value will then be decremented on the second
active clock edge to arrive after the write (i.e., after
the first complete period of the clock). When the
timer counter under flows (i.e., reaches 0), it will
assert its appropriate interrupt. The timer counters
can be read at any time. The clock source and mode
are selectable by writing to various bits in the sys-
tem control register. When run from the internal
PLL, 512 kHz and 2 kHz rates are provided. When
using the 13 MHz external source, the default fre-
quencies will be 541 kHz and 2.115 kHz, respec-
tively. However, only in non-PLL mode, an
optional divide by 26 frequency can be generated
(thus generating a 500 kHz frequency when using
the 13 MHz source). This divider is enabled by set-
ting the OSTB (Operating System Timing Bit) in
the SYSCON2 register (bit 12). When this bit is set
high to select the 500 kHz mode, the 500 kHz fre-
quency is routed to the timers instead of the
541 kHz clock. This does not affect the frequencies
derived for any of the other internal peripherals.
The timer counters can operate in two modes: free
running or pre-scale.
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