EP7212 Datasheet, PDF (58/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.1.4 PADDR Port A Data Direction Register
ADDRESS: 0x8000.0040
Bits set in this 8-bit read / write register will select the corresponding pin in Port A to become an output,
clearing a bit sets the pin to input. All bits are cleared by a system reset.
5.1.5 PBDDR Port B Data Direction Register
ADDRESS: 0x8000.0041
Bits set in this 8-bit read / write register will select the corresponding pin in Port B to become an output,
clearing a bit sets the pin to input. All bits are cleared by a system reset.
5.1.6 PDDDR Port D Data Direction Register
ADDRESS: 0x8000.0043
Bits cleared in this 8-bit read / write register will select the corresponding pin in Port D to become an
output, setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output
by default.
5.1.7 PEDR Port E Data Register
ADDRESS: 0x8000.0080
Values written to this 3-bit read / write register will be output on Port E pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
E, not necessarily the value written to it. All bits are cleared by a system reset.
5.1.8 PEDDR Port E Data Direction Register
ADDRESS: 0x8000.00C0
Bits set in this 3-bit read / write register will select the corresponding pin in Port E to become an output,
while the clearing bit sets the pin to input. All bits are cleared by a system reset so that Port E is input
by default.
5.2 SYSTEM Control Registers
5.2.1 SYSCON1 The System Control Register 1
ADDRESS: 0x8000.0100
23
22
17:16
ADCKSEL
7
TC2S
15
SIREN
6
TC2M
21
14
CDENRX
5
TC1S
20
IRTXM
13
CDENTX
4
TC1M
19
WAKEDIS
12
LCDEN
3:0
Keyboard scan
18
EXCKEN
11
DBGEN
The system control register is a 21-bit read / write register which controls all the general configuration
of the EP7212, as well as modes etc. for peripheral devices. All bits in this register are cleared by a
system reset. The bits in the system control register SYSCON1 are defined in Table 29.
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