EP7212 Datasheet, PDF (6/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
3.13.1 Codec Sound Interface .......................................................................................... 39
3.13.2 Digital Audio Interface ............................................................................................ 40
3.13.2.1 DAI Operation ............................................................................................ 41
3.13.2.2 DAI Frame Format ..................................................................................... 41
3.13.2.3 DAI Signals ................................................................................................ 42
3.13.3 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) ........... 42
3.13.4 Master / Slave SSI2 (Synchronous Serial Interface 2) .......................................... 43
3.13.4.1 Read Back of Residual Data ..................................................................... 44
3.13.4.2 Support for Asymmetric Traffic .................................................................. 45
3.13.4.3 Continuous Data Transfer ......................................................................... 45
3.13.4.4 Discontinuous Clock .................................................................................. 45
3.13.4.5 Error Conditions ......................................................................................... 46
3.13.4.6 Clock Polarity ............................................................................................. 46
3.14 LCD Controller with Support for On-Chip Frame Buffer .................................................. 46
3.15 Timer Counters ............................................................................................................... 47
3.15.1 Free Running Mode ............................................................................................... 48
3.15.2 Prescale Mode ....................................................................................................... 48
3.16 Real Time Clock .............................................................................................................. 49
3.16.1 Characteristics of the Real Time Clock Interface ................................................... 49
3.17 Dedicated LED Flasher ................................................................................................... 49
3.18 Two PWM Interfaces ....................................................................................................... 49
3.19 Boundary Scan ................................................................................................................ 50
3.20 In-Circuit Emulation ......................................................................................................... 50
3.20.1 Introduction ............................................................................................................ 50
3.20.2 Functionality ........................................................................................................... 51
3.21 Maximum EP7212-Based System .................................................................................. 51
4. MEMORY MAP ....................................................................................................................... 53
5. REGISTER DESCRIPTIONS .................................................................................................. 54
5.1 Internal Registers .............................................................................................................. 54
5.1.1 PADR Port A Data Register ..................................................................................... 57
5.1.2 PBDR Port B Data Register ..................................................................................... 57
5.1.3 PDDR Port D Data Register .................................................................................... 57
5.1.4 PADDR Port A Data Direction Register ................................................................... 58
5.1.5 PBDDR Port B Data Direction Register ................................................................... 58
5.1.6 PDDDR Port D Data Direction Register ................................................................... 58
5.1.7 PEDR Port E Data Register ..................................................................................... 58
5.1.8 PEDDR Port E Data Direction Register ................................................................... 58
5.2 SYSTEM Control Registers ............................................................................................... 58
5.2.1 SYSCON1 The System Control Register 1 ............................................................. 58
5.2.2 SYSCON2 System Control Register 2 ..................................................................... 61
5.2.3 SYSCON3 System Control Register 3 ..................................................................... 63
5.2.4 SYSFLG1 — The System Status Flags Register .................................................... 64
5.2.5 SYSFLG2 System Status Register 2 ....................................................................... 66
5.3 Interrupt Registers ............................................................................................................. 67
5.3.1 INTSR1 Interrupt Status Register 1 ......................................................................... 67
5.3.2 INTMR1 Interrupt Mask Register 1 .......................................................................... 68
5.3.3 INTSR2 Interrupt Status Register 2 ......................................................................... 69
5.3.4 INTMR2 Interrupt Mask Register 2 .......................................................................... 69
5.3.5 INTSR3 Interrupt Status Register 3 ......................................................................... 70
5.3.6 INTMR3 Interrupt Mask Register 3 .......................................................................... 70
5.4 Memory Configuration Registers ....................................................................................... 71
5.4.1 MEMCFG1 Memory Configuration Register 1 ......................................................... 71
5.4.2 MEMCFG2 Memory Configuration Register 2 ......................................................... 71
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DS474PP1