EP7212 Datasheet, PDF (60/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
Bit
11
12
13
14
15
16:17
18
19
20
60
Description
DBGEN: Setting this bit will enable the debug mode. In this mode, all internal accesses are out-
put as if they were reads or writes to the expansion memory addressed by nCS5. nCS5 will still
be active in its standard address range. In addition, the internal interrupt request and fast inter-
rupt request signals to the ARM720T processor are output on Port E, bits 1 and 2. Note that
these bits must be programmed to be outputs before this functionality can be observed. The
clock to the CPU is output on Port E, Bit 0 to delineate individual accesses. For example, in
debug mode:
nCS5 = nCS5 or internal I/O strobe
PE0 = CLK
PE1 = nIRQ
PE2 = nFIQ
LCDEN: LCD enable bit. Setting this bit enables the LCD controller.
CDENTX: Codec interface enable TX bit. Setting this bit enables the codec interface for data
transmission to an external codec device.
CDENRX: Codec interface enable RX bit. Setting this bit enables the codec interface for data
reception from an external codec device.
NOTE: Both CDENRX and CDENTX need to be enabled / disabled in tandem, otherwise data may
be lost.
SIREN: HP SIR protocol encoding enable bit. This bit will have no effect if the UART is not
enabled.
ADCKSEL: Microwire / SPI peripheral clock speed select. This two-bit field selects the frequency
of the ADC sample clock, which is twice the frequency of the synchronous serial ADC interface
clock. The table below shows the available frequencies for operation when in PLL mode. These
bits are also used to select the shift clock frequency for the SSI2 interface when set into master
mode. The frequencies obtained in 13.0 MHz mode can be found in Table 23.
ADCKSEL
00
01
10
11
ADC Sample Frequency
(kHz) — SMPCLK
8
32
128
256
ADC Clock Frequency
(kHz) — ADCCLK
4
16
64
128
EXCKEN: External expansion clock enable. If this bit is set, the EXPCLK is enabled continuously
as a free running clock with the same frequency and phase as the CPU clock, assuming that the
main oscillator is running. This bit should not be left set all the time for power consumption rea-
sons. If the system enters the Standby State, the EXPCLK will become undefined. If this bit is
clear, EXPCLK will be active during memory cycles to expansion slots that have external wait
state generation enabled only.
WAKEDIS: Setting this bit disables waking up from the Standby State, via the wakeup input.
IRTXM: IrDA TX mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means
that each zero bit transmitted is represented as a pulse of width 3/16th of the bit rate period. Set-
ting this bit means each zero bit is represented as a pulse of width 3/16th of the period of
115,200-bit rate clock (i.e., 1.6 µsec regardless of the selected bit rate). Setting this bit will use
less power, but will probably reduce transmission distances.
Table 29. SYSCON1 (cont.)
DS474PP1