EP7212 Datasheet, PDF (46/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
3.13.4.5 Error Conditions
RX FIFO overflows are detected and conveyed via
a status bit in the SYSFLG2 register. This register
should be accessed at periodic intervals by the ap-
plication software. The status register should be
read each time the RX FIFO interrupts are generat-
ed. At this time the error condition (i.e., overrun
flag) will indicate that an error has occurred but
cannot convey which byte contains the error. Writ-
ing to the SRXEOF register location clears the
overrun flag. TX FIFO underflow condition is de-
tected and conveyed via a bit in the SYSFLG2 reg-
ister, which is accessed by the application software.
A TX underflow error is cleared by writing data to
be transmitted to the TX FIFO.
3.13.4.6 Clock Polarity
Clock polarity is fixed. TX data is presented on the
bus on the rising edge of the clock. Data is latched
into the receiving device on the falling edge of the
clock. The TX pin is held in a tristate condition
when not transmitting.
3.14 LCD Controller with Support for On-
Chip Frame Buffer
The LCD controller provides all the necessary con-
trol signals to interface directly to a single panel
multiplexed LCD. The panel size is programmable
and can be any width (line length) from 32 to
1024 pixels in 16-pixel increments. The total video
frame buffer size is programmable up to 128
kbytes. This equates to a theoretical maximum pan-
el size of 1024 x 256 pixels in 4 bits-per-pixel
mode. The video frame buffer can be located in any
portion of memory controlled by the chip selects.
Its start address will be fixed at address 0x0000000
within each chip select. The start address of the
LCD video frame buffer is defined in the FBAD-
DR[3:0] register. These bits become the most sig-
nificant nibble of the external address bus. The
default start address is 0xC000 0000 (FBADDR =
0xC). A system built using the on-chip SRAM
(OCSR), will then serve as the LCD video frame
buffer and miscellaneous data store. The LCD vid-
eo frame buffer start address should be set to 0x6 in
this option. Programming of the register FBADDR
is only permitted when the LCD is disabled (this is
to avoid possible cycle corruption when changing
the register contents while a LCD DMA cycle is in
progress). There is no hardware protection to pre-
vent this. It is necessary for the software to disable
the LCD controller before reprogramming the
FBADDR register. Full address decoding is pro-
vided for the OCSR, up to the maximum video
frame buffer size programmable into the LCDCON
register. Beyond this, the address is wrapped
around. The frame buffer start address must not be
programmed to 0x4 or 0x5 if either CL-PS6700 in-
terface is in use (PCMEN1 or PCMEN2 bits in the
SYSCON2 register are enabled). FBADDR should
never be programmed to 0x7 or 0x8, as these are
the locations for the on-chip Boot ROM and inter-
nal registers.
The screen is mapped to the video frame buffer as
one contiguous block where each horizontal line of
pixels is mapped to a set of consecutive bytes or
words in the video RAM. The video frame buffer
can be accessed word wide as pixel 0 is mapped to
the LSB in the buffer such that the pixels are ar-
ranged in a little endian manner.
The pixel bit rate, and hence the LCD refresh rate,
can be programmed from 18.432 MHz to 576 kHz
when operating in 18.432–73.728 MHz mode, or
13 MHz to 203 kHz when operating from a
13 MHz clock. The LCD controller is programmed
by writing to the LCD control register (LCDCON).
The LCDCON register should not be repro-
grammed while the LCD controller is enabled.
The LCD controller also contains two 32-bit palette
registers, which allow any 4-, 2-, or 1-bit pixel val-
ue to be mapped to any of the 15 grayscale values
available. The required DMA bandwidth to support
a ½ VGA panel displaying 4 bits-per-pixel data at
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