EP7212 Datasheet, PDF (91/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

5.16.2.3 DAIDR2 DAI Data Register 2
ADDRESS: 0x8000.20C0
31:21
Reserved
20:16
FIFO Channel Select
15
FIFOEN
EP7212
14:0
Reserved
DAIDR2 is a 32-bit register that utilizes 21 bits and is used to enable and disable the FIFOs for the
left and right channels of the DAI data stream. The left channel FIFO is enabled by writing
0x000D.8000 and disabled by writing 0x000D.0000. The right channel FIFO is enabled by writing
0x0011.8000 and disabled by writing 0x0011.0000. After writing a value to this register, wait until the
FIFO operation complete bit (FIFO) is set in the DAI status register before writing another value to this
register.
Bit
0:14
15
16:20
21:31
Reserved
FIFOEN: FIFO Transmit Bit
0 — Disable Transmit
1 — Enable Transmit
FIFO CHANNEL SELECT:
01101b — Left channel select
10001b — Right channel select
Reserved
Description
Table 53. DAI Data Register 2
DS474PP1
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