EP7212 Datasheet, PDF (9/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
LIST OF FIGURES
Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ............................................ 13
Figure 2. EP7212 Block Diagram.................................................................................................. 20
Figure 3. State Diagram ................................................................................................................ 21
Figure 4. CLKEN Timing Entering the Standby State ................................................................... 26
Figure 5. CLKEN Timing Entering the Standby State ................................................................... 26
Figure 6. Codec Interrupt Timing .................................................................................................. 40
Figure 7. DAI Interface .................................................................................................................. 41
Figure 8. EP7212 Rev C - Digital Audio Interface Timing – MSB / Left Justified format............... 42
Figure 9. SSI2 Port Directions in Slave and Master Mode............................................................ 44
Figure 10. Residual Byte Reading ................................................................................................ 45
Figure 11. Video Buffer Mapping .................................................................................................. 48
Figure 12. A Maximum EP7212 Based System ............................................................................ 52
Figure 13. Consecutive Memory Read Cycles with Minimum Wait States ................................. 100
Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States............................... 101
Figure 15. Consecutive Memory Write Cycles with Minimum Wait States.................................. 102
Figure 16. DRAM Read Cycles at 13 MHz and 18.432 MHz ...................................................... 103
Figure 17. DRAM Read Cycles at 36 MHz.................................................................................. 104
Figure 18. DRAM Write Cycles at 13 MHz and 18 MHz ............................................................. 105
Figure 19. DRAM Write Cycles at 36 MHz.................................................................................. 106
Figure 20. Video Quad Word Read from DRAM at 13 MHz and 18 MHz ................................... 107
Figure 21. Quad Word Read from DRAM at 36 MHz.................................................................. 107
Figure 22. DRAM CAS Before RAS Refresh Cycle at 13 MHz and 18 MHz............................... 108
Figure 23. DRAM CAS Before RAS Refresh Cycle at 36 MHz ................................................... 109
Figure 24. LCD Controller Timings.............................................................................................. 109
Figure 25. SSI Interface for AD7811/2 ........................................................................................ 110
Figure 26. SSI2 Interface Timings............................................................................................... 110
Figure 27. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ........................................ 116
Figure 28. 256-Ball Plastic Ball Grid Array Diagram ................................................................... 120
LIST OF TABLES
Table 1. Acronyms and Abbreviations .......................................................................................... 11
Table 2. Unit of Measurement....................................................................................................... 12
Table 3. Pin Description Conventions ........................................................................................... 12
Table 4. External Signal Functions ............................................................................................... 14
Table 5. SSI/Codec/DAI Pin Multiplexing...................................................................................... 18
Table 6. Output Bi-Directional Pins ............................................................................................... 18
Table 7. Peripheral Status in Different Power Management States.............................................. 22
Table 8. Exception Priority Handling ............................................................................................. 27
Table 9. Interrupt Allocation in the First Interrupt Register............................................................ 28
Table 10. Interrupt Allocation in the Second Interrupt Register .................................................... 28
Table 11. Interrupt Allocation in the Third Interrupt Register ........................................................ 28
Table 12. External Interrupt Source Latencies.............................................................................. 30
Table 13. Chip Select Address Ranges After Boot From On-Chip Boot ROM.............................. 30
Table 14. Boot Options ................................................................................................................. 31
Table 15. Physical to DRAM Address Mapping ............................................................................ 32
Table 16. DRAM Address Mapping When Connected to an External 32-Bit DRAM
Memory System ............................................................................................................... 33
Table 17. CL-PS6700 Memory Map.............................................................................................. 34
Table 18. Space Field Decoding ................................................................................................... 34
DS474PP1
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