EP7212 Datasheet, PDF (73/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
Bit
6
7
Description
SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a
quad word boundary to take advantage of faster access times from devices that support page
mode. The sequential access will be faulted after four words (to allow video refresh cycles to
occur), even if the access is part of a longer sequential access. In addition, when this bit is not
set, non-sequential accesses will have a single idle cycle inserted at least every four cycles so
that the chip select is de-asserted periodically between accesses for easier debug.
CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during
accesses to the selected expansion device. This will provide a timing reference for devices that
need to extend bus cycles using the EXPRDY input. Back-to-back (but not necessarily page
mode) accesses will result in a continuous clock. This bit will only affect EXPCLK when the PLL
is being used (i.e., in 73.728–18.432 MHz mode). When operating in 13 MHz mode, the EXPCLK
pin is an input, so it is not affected by this register bit. To save power internally, it should always
be set to zero when operating in 13 MHz mode.
Table 40. MEMCFG
See the AC Electrical Specification section for more detail on bus timing.
The memory area decoded by CS[6] is reserved for the on-chip SRAM, hence this does not require
a configuration field in MEMCFG2. It is automatically set up for 32-bit-wide, no-wait-state accesses.
For the Boot ROM, it is automatically set up for 8-bit, no wait state accesses.
Chip selects nCS[4] and nCS[5] are used to select two CL-PS6700 PC CARD controller devices.
These have a multiplexed 16-bit wide address / data interface, and the configuration bytes in the
MEMCFG2 register have no meaning when these interfaces are enabled.
DS474PP1
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