EP7212 Datasheet, PDF (24/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
1). Upon power, the signal nPOR must be held ac-
tive (LOW) for a minimum of 100us, after V_DD has
become settled.
2). After nPOR goes HIGH, the EP7212 will enter
the Standby State (and only this state). In this state,
the PLL is not enabled, and thus the CPU is not en-
abled either. The only method that can be used to
allow the EP7212 to exit the Standby State into the
Operating State is by the WAKEUP signal going
active (HIGH).
NOTE:
It is not a requirement to use the nURESET
signal. If not used, the nURESET signal
must be HIGH, and it must have gone HIGH
prior to nPOR going HIGH. This is due to the
fact that nURESET is latched into the device
by the rising edge of nPOR. When nURE-
SET is LOW on the rising edge of nPOR, it
can force the device into one of its Test
Mode states.
3). After nPOR goes HIGH, the WAKEUP signal
cannot be detected as going HIGH, until after at
least two seconds. After two seconds, the WAKE-
UP signal can become active, and it must be HIGH
for at least 125us.
4). After the WAKEUP signal is detected internal-
ly, it first goes through a deglitching circuit. This is
why is must be active for at least 125us. Then the
PLL gets enabled. WAKEUP is ignored immedi-
ately after waking up the system. It also ignores it
while in the Idle or Operating State. It can constant-
ly toggle with no affect on the device. It will only
be read again if nPOR goes low and then high
again, or if software has forced the device back into
the Standby State.
5). A maximum of 250 msec will pass before the
CPU becomes enabled and starts to fetch the first
instruction.
3.4 Resets
There are three asynchronous resets to the EP7212:
nPOR, nPWRFL and nURESET. If any of these are
active, a system reset is generated internally. This
will reset all internal registers in the EP7212 except
the RTC data and match registers. These registers
are only cleared by nPOR allowing the system time
to be preserved through a user reset or power fail
condition.
Any reset will also reset the CPU and cause it to
start execution at the reset vector when the EP7212
returns to the Operating State.
Internal to the EP7212, three different signals are
used to reset storage elements. These are nPOR,
nSYSRES and nSTBY. nPOR is an external signal.
nSTBY is equivalent to the external RUN signal.
nPOR (Power On Reset, active low) is the highest
priority reset signal. When active (low), it will reset
all storage elements in the EP7212. nPOR active
forces nSYSRES and nSTBY active. nPOR will
only be active after the EP7212 is first powered up
and not during any other resets. nPOR active will
clear all flags in the status register except for the
cold reset flag (CLDFLG) bit (SYSFLG, bit 15),
which is set.
nSYSRES (System Reset, active low) is generated
internally to the EP7212 if nPOR, nPWRFL, or
nURESET are active. It is the second highest prior-
ity reset signal, used to asynchronously reset most
internal registers in the EP7212. nSYSRES active
forces nSTBY and RUN low. nSYSRES is used to
reset the EP7212 and force it into the Standby State
with no co-operation from software. The CPU is
also reset.
The nSTBY and RUN signals are high when the
EP7212 is in the Operating or Idle States and low
when in the Standby State. The main system clock
is valid when nSTBY is high. The nSTBY signal
will disable any peripheral block that is clocked
from the master clock source (i.e., everything ex-
cept for the RTC). In general, a system reset will
clear all registers and nSTBY will disable all pe-
ripherals that require a main clock. The following
peripherals are always disabled by a low level on
nSTBY: two UARTs and IrDA SIR encoder, timer
counters, telephony codec, and the two SSI inter-
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