EP7212 Datasheet, PDF (70/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.3.5 INTSR3 Interrupt Status Register 3
ADDRESS: 0x8000.2240
7:1
Reserved
0
DAIINT
This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of the
EP7212. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in
Table 36.
Bit
0
Description
DAIINT: DAI interface interrupt. The cause must be determined by reading the DAI status regis-
ter. It is mapped to the FIQ interrupt on the ARM720T processor
Table 36. INTSR3
5.3.6 INTMR3 Interrupt Mask Register 3
ADDRESS: 0x8000.2280
7:1
Reserved
0
DAIINT
This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the new fea-
tures of the EP7212. Please refer to INTSR3 for individual bit details.
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