EP7212 Datasheet, PDF (23/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
2) Ensure that on entry to the Standby State, the
chosen interrupt source is not masked, and the
UART is enabled.
3) Send a preamble that consists of one start bit,
8 bits of zero, and one stop bit. This will cause
the EP7212 to wake and execute the enabled in-
terrupt vector.
The UART will automatically be re-enabled when
the processor re-enters the Operating State, and the
preamble will be received. Since the UART was
not awake at the start of the preamble, the timing of
the sample point will be off-center during the pre-
amble byte. However, the next byte transmitted
will be correctly aligned. Thus, the actual first real
byte to be received by the UART will get captured
correctly.
3.2.2 Idle State
If in the Operating State, the Idle State can be en-
tered by writing to a special internal memory loca-
tion (HALT) in the EP7212. If an interrupt occurs,
the EP7212 will return immediately back to the Op-
erating State and execute the next instruction. The
WAKEUP signal can not be used to exit the Idle
State. It is only used to exit the Standby State.
In the Idle State, the device functions just like it
does when in the Operating State. However, the
CPU clock is halted while it waits for an event such
as a key press to generate an interrupt. The PLL (in
18.432–73.728 MHz mode) or the external
13 MHz clock source always remains active in the
Idle State.
3.2.3 Keyboard Interrupt
For the case of the keyboard interrupt, the follow-
ing options are available and are selectable accord-
ing to bits 1 and 3 of the SYSCON2 register (refer
to the SYSCON2 Register Description for details).
• If the KBWEN bit (SYSCON2 bit 3) is set low,
then a keypress will cause a transition from a
power saving state only if the keyboard inter-
rupt is non-masked (i.e., the interrupt mask reg-
ister 2 (INTMR2 bit 0) is high).
• When KBWEN is high, a keypress will cause
the device to wake up regardless of the state of
the interrupt mask register. This is called the
“Keyboard Direct Wakeup’ mode. In this
mode, the interrupt request may not get ser-
viced. If the interrupt is masked (i.e., the inter-
rupt mask register 2 (INTMR2 bit 0) is low),
the processor simply starts re-executing code
from where it left off before it entered the pow-
er saving state. If the interrupt is non-masked,
then the processor will service the interrupt.
• When the KBD6 bit (SYSCON2 bit 1) is low,
all 8 of Port A inputs are OR’ed together to pro-
duce the internal wakeup signal and keyboard
interrupt request. This is the default reset state.
• When the KBD6 bit (SYSCON2 bit 1) is high,
only the lowest 6 bits of Port A are OR’ed to-
gether to produce the internal wakeup signal
and keyboard interrupt request. The two most
significant bits of Port A are available as GPIO
when this bit is set high.
In the case where KBWEN is low and the INTMR2
bit 0 is low, it will only be possible to wakeup the
device by using the external WAKEUP pin or an-
other enabled interrupt source. The keyboard inter-
rupt capability allows an OS to use either a polled
or interrupt-driven keyboard routine, or a combina-
tion of both.
NOTE: The keyboard interrupt is NOT deglitched.
3.3 Power-Up Sequence
The EP7212 has a power-up sequence that should
be followed for proper start up. If any of the below
recommended timing sequences are violated, then
it is possible that the part may not start-up properly.
This could cause the device to get lost and not re-
cover without a hard reset.
DS474PP1
23