EP7212 Datasheet, PDF (38/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
UART operation and line speeds are controlled by
the UBLCR1 (UART bit rate and line control).
Three interrupts can be generated by UART1: RX,
TX, and modem status interrupts. Only two can be
generated by UART2: RX and TX. The RX inter-
rupt is asserted when the RX FIFO becomes half
full or if the FIFO is non-empty for longer than
three character length times with no more charac-
ters being received. The TX interrupt is asserted if
the TX FIFO buffer reaches half empty. The mo-
dem status interrupt for UART1 is generated if any
of the modem status bits change state. Framing and
parity errors are detected as each byte is received
and pushed onto the RX FIFO. An overrun error
generates an RX interrupt immediately. All error
bits can be read from the 11-bit wide data register.
The FIFOs can also be programmed to be one byte
depth only (i.e., like a conventional 16450 UART
with double buffering).
The EP7212 also contains an IrDA (Infrared Data
Association) SIR protocol encoder as a post-pro-
cessing stage on the output of UART1. This encod-
er can be optionally switched into the TX and RX
signals of UART1, so that these can be used to
drive an infrared interface directly. If the SIR pro-
tocol encoder is enabled, the UART TXD1 line is
held in the passive state and transitions of the
RXD1 line will have no effect. The IrDA output pin
is LEDDRV, and the input from the photodiode is
PHDIN. Modem status lines will cause an interrupt
(which can be masked) irrespective of whether the
SIR interface is being used.
Both the UARTs operate in a similar manner to the
industry standard 16C550A. When CTS is deas-
serted on the UART, the UART does not stop shift-
ing the data. It relies on software to take
appropriate action in response to the interrupt gen-
erated.
Baud rates supported for both the UARTs are de-
pendent on frequency of operation. When operat-
ing from the internal PLL, the interface supports
various baud rates from 115.2 kbits/s downwards.
The master clock frequency is chosen so that most
of the required data rates are obtainable exactly.
When operating with a 13.0 MHz external clock
source, the baud rates generated will have a slight
error, which is less than or equal to 0.75%. The
rates (all measured in kbits/s) obtainable from the
13 MHz clock include: 9.6, 19.2, 38, 58, and 115.2.
See UBRLCR1-2 UART1-2 Bit Rate and Line Con-
trol Registers for full details of the available bit
rates in the 13 MHz mode.
3.13 Serial Interfaces
In addition to the two UARTs, the EP7212 offers
the following serial interfaces shown in Table 21.
The inputs / outputs of three of the serial interfaces
(DAI, codec, and SSI2) are multiplexed onto a sin-
gle set of external interface pins. If the DAISEL bit
of SYSCON3 is low, then either SSI2 or the codec
interface will be selected to connect to the external
pins. When bit 0 of SYSCON2 (SERSEL) is high,
then the codec is connected to the external pins,
when low the master / slave SSI2 is connected to
these pins. When the DAISEL bit is set high, the
DAI interface is connected to the external pins. On
power up, both the DAISEL and SERSEL bits are
reset low, thus the master / slave SSI2 will be con-
nected to these pins (and configured for slave mode
operation to avoid external drive clashes).
Table 22 contains pin definition information for the
three multiplexed interfaces.
The internal names given to each of the three inter-
faces are unique to help differentiate them from
each other. The sections below that describe each
of the three interfaces will use their respective
unique internal pin names for clarity.
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