EP7212 Datasheet, PDF (81/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.10.3 PALMSW Most Significant Word — LCD Palette Register
ADDRESS: 0x8000.0540
31:28
Grayscale
value for pixel
value 15
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Grayscale Grayscale Grayscale Grayscale Grayscale Grayscale Grayscale
value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel
value 14
value 13
value 12
value 11
value 10
value 9
value 8
The pixel to grayscale level assignments and the actual physical color and pixel duty ratio for the gray-
scale values are shown in Table 48. Note that colors 8–15 are the inverse of colors 7–0 respectively.
This means that colors 7 and 8 are identical. Therefore, in reality only 15 grayscales available, not 16.
The steps in the grayscale are non-linear, but have been chosen to give a close approximation to per-
ceived linear grayscales. The is due to the eye being more sensitive to changes in gray level close to
50% gray (See PALLSW description).
Grayscale Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Duty Cycle
0
1/9
1/5
4/15
3/9
2/5
4/9
1/2
1/2
5/9
3/5
6/9
11/15
4/5
8/9
1
% Pixels Lit
0%
11.1%
20.0%
26.7%
33.3%
40.0%
44.4%
50.0%
50.0%
55.6%
60.0%
66.7%
73.3%
80.0%
88.9%
100%
% Step Change
11.1%
8.9%
6.7%
6.6%
6.7%
5.4%
5.6%
0.0%
5.6%
5.4%
6.7%
6.6%
6.7%
8.9%
11.1%
Table 48. Grayscale Value to Color Mapping
5.10.4 FBADDR LCD Frame Buffer Start Address
ADDRESS: 0x8000.1000
This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer
starts at location 0x0000000 within each chip select memory region. Therefore, the value stored with-
in the FBADDR register is only the value of the chip select where the frame buffer is located. On reset,
this will be set to 0xC. The register is 4 bits wide (bits [3:0]). This register must only be reprogrammed
when the LCD is disabled (i.e., setting the LCDEN bit within SYSCON2 low).
DS474PP1
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