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EP7212 Datasheet, PDF (55/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212
Address
0x8000.0000
0x8000.0001
0x8000.0002
0x8000.0003
0x8000.0040
0x8000.0041
0x8000.0042
0x8000.0043
0x8000.0080
0x8000.00C0
0x8000.0100
0x8000.0140
0x8000.0180
0x8000.01C0
0x8000.0200
0x8000.0240
0x8000.0280
0x8000.02C0
0x8000.0300
0x8000.0340
0x8000.0380
0x8000.03C0
0x8000.0400
0x8000.0440
0x8000.0480
0x8000.04C0
0x8000.0500
0x8000.0540
0x8000.0580
0x8000.05C0
0x8000.0600
0x8000.0640
0x8000.0680
0x8000.06C0
0x8000.0700
Name Default RD/WR Size
Comments
PADR
0
RW 8 Port A data register
PBDR
0
RW 8 Port B data register
—
— 8 Reserved
PDDR
0
RW 8 Port D data register
PADDR
0
RW 8 Port A data direction register
PBDDR
0
RW 8 Port B data direction register
—
— 8 Reserved
PDDDR
0
RW 8 Port D data direction register
PEDR
0
RW 3 Port E data register
PEDDR
0
RW 3 Port E data direction register
SYSCON1 0
RW 32 System control register 1
SYSFLG1
0
RD 32 System status flags register 1
MEMCFG1 0
RW 32 Expansion memory configuration register 1
MEMCFG2 0
RW 32 Expansion memory configuration register 2
DRFPR
0
RW 8 DRAM refresh period register
INTSR1
0
RD 32 Interrupt status register 1
INTMR1
0
RW 32 Interrupt mask register 1
LCDCON
0
RW 32 LCD control register
TC1D
0
RW 16 Read / Write register sets and reads data to TC1
TC2D
0
RW 16 Read / Write register sets and reads data to TC2
RTCDR
—
RW 32 Real Time Clock data register
RTCMR
—
RW 32 Real Time Clock match register
PMPCON
0
RW 12 PWM pump control register
CODR
0
RW 8 CODEC data I/O register
UARTDR1 0
RW 16 UART1 FIFO data register
UBLCR1
0
RW 32 UART1 bit rate and line control register
SYNCIO
0
RW 32 Synchronous serial I/O data register for master
only SSI
PALLSW
0
RW 32 Least significant 32-bit word of LCD palette register
PALMSW
0
RW 32 Most significant 32-bit word of LCD palette register
STFCLR
—
WR — Write to clear all start up reason flags
BLEOI
—
WR — Write to clear battery low interrupt
MCEOI
—
WR — Write to clear media changed interrupt
TEOI
—
WR — Write to clear tick and watchdog interrupt
TC1EOI
—
WR — Write to clear TC1 interrupt
TC2EOI
—
WR — Write to clear TC2 interrupt
Table 27. EP7212 Internal Registers (Little Endian Mode)
DS474PP1
55