EP7212 Datasheet, PDF (18/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
2.2.2 SSI/Codec/DAI Pin Multiplexing
SSI2
Codec
SSICLK
PCMCLK
SSITXFR
PCMSYNC
SSITXDA
PCMOUT
SSIRXDA
PCMIN
SSIRXFR
p/u*
* p/u = use an ~10 k pull-up
DAI
SCLK
LRCK
SDOUT
SDIN
MCLK
Direction
I/O
I/O
Output
Input
I/O
Strength
1
1
1
1
The selection between SSI2 and the codec is controlled by the state of the SERSEL bit in SYSCON2 (See
SYSCON2 System Control Register 2). The choice between the SSI2, codec, and the DAI is controlled by
the DAISEL bit in SYSCON3 (See SYSCON3 System Control Register 3).
Table 5. SSI/Codec/DAI Pin Multiplexing
2.2.3 Output Bi-Directional Pins
RUN
nCAS[3:0]
Drive [0-1]
DD[3:0]
The RUN pin is looped back in to skew the address and data bus from each other.
The nCAS pins are looped back into the EP7212 to be used as the actual clock source for the data to be
latched internally.
Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be
when active.
DD[3:0] are looped back in on power up to enable the reading of the ID of some LCD modules.
NOTE:
The above output pins are implemented as bi-directional pins to enable the output side of the pad to
be monitored and hence provide more accurate control of timing or duration.
Table 6. Output Bi-Directional Pins
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