EP7212 Datasheet, PDF (80/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
Bit
19:24
25:29
30
31
Description
Pixel prescale: The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel
rate is always derived from a 36.864 MHz clock when in PLL mode, and is calculated from the
formula:
Pixel rate (MHz) = 36.864 / (Pixel prescale + 1)
When the EP7212 is operating at 13 MHz, pixel rate is given by the formula:
Pixel rate (MHz) = 13 / (Pixel prescale + 1)
The pixel prescale value can be expressed in terms of the LCD size by the formula:
When the EP7212 is operating @ 18.432 MHz:
Pixel prescale = (36864000 / (Refresh Rate x Total pixels in display)) – 1
When the EP7212 is operating @ 13 MHz:
Pixel prescale = (13000000 / (Refresh Rate x Total pixels in display)) – 1
Refresh Rate is the screen refresh frequency (70 Hz to avoid flicker)
The value should be rounded down to the nearest whole number and zero is illegal and will result
in no pixel clock.
EXAMPLE: For a system being operated in the 18.432–73.728 MHz mode, with a 640 x 240
screen size, and 70 Hz screen refresh rate desired, the LCD Pixel prescale equals 36.864E6 /
(70 x 640x240) – 1 = 2.428
Rounding 2.428 down to the nearest whole number equals 2.
This gives an actual pixel rate of 36.864E6 / (2+1) = 12.288 MHz, which gives an actual refresh
frequency of 12.288E6 / (640x240) = 80 Hz.
NOTE: As the CL[2] low pulse time is doubled after every CL[1] high pulse this refresh fre-
quency is only an approximation, the accurate formula is 12.288E6 / ((640x240)+120)
= 79.937 Hz.
AC prescale: The AC prescale field is a 5-bit number that sets the LCD AC bias frequency. This
frequency is the required AC bias frequency for a given manufacturer’s LCD plate. This fre-
quency is derived from the frequency of the line clock (CL[1]). The LCD M signal will toggle after
n+1 counts of the line clock (CL[1]) where n is the number programmed into the AC prescale
field. This number must be chosen to match the manufacturer’s recommendation. This is nor-
mally 13, but must not be exactly divisible by the number of lines in the display.
GSEN: Grayscale enable bit. Setting this bit enables grayscale output to the LCD. When this bit
is cleared, each bit in the video map directly corresponds to a pixel in the display.
GSMD: Grayscale mode bit. Clearing this bit sets the controller to 2 bits-per-pixel (4 grayscale),
setting it sets it to 4 bits-per-pixel (16 grayscale). This bit has no effect if GSEN is cleared.
Table 47. LCDCON (cont.)
5.10.2 PALLSW Least Significant Word — LCD Palette Register
ADDRESS: 0x8000.0580
31:28
27:24
23:20
19:16
15:12
11:8
7:4
3:0
Grayscale
Grayscale Grayscale Grayscale Grayscale Grayscale Grayscale Grayscale
value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel
value 7
value 6
value 5
value 4
value 3
value 2
value 1
value 0
The least and most significant word LCD palette registers make up a 64-bit read / write register which
maps the logical pixel value to a physical grayscale level. The 64-bit register is made up of 16 x 4-bit
nibbles, each nibble defines the grayscale level associated with the appropriate pixel value. If the LCD
controller is operating in two bits-per-pixel, only the lower 4 nibbles are valid (D[15:0] in the least sig-
nificant word). Similarly, one bit-per-pixel means only the lower 2 nibbles are valid (D[7:0]) in the least
significant word.
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DS474PP1