EP7212 Datasheet, PDF (26/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
The output clock pin (i.e., MOSCOUT) should be
left floating.
3.5.2 External Clock Input (13 MHz)
An external 13 MHz crystal oscillator can be used
to drive all of the EP7212. When selected the
ARM720T and the address/data buses both get
clocked at 13 MHz. The fixed clock sources to the
various peripherals will have different frequencies
than in the PLL mode. In this configuration, the
PLL will not be used at all.
NOTE:
When operating at 13 MHz, the
CLKCTL[1:0] bits should not be changed
from their default value of ‘00’.
3.5.3 Dynamic Clock Switching When in the
PLL Clocking Mode
The clock frequency used for the CPU and the bus-
es is controlled by programming the CLKCTL[1:0]
bits in the SYSCON3 register. When this occurs,
the state controller switches from the current to the
new clock frequency as soon as possible without
causing a glitch on the clock signals. The glitch-
free clock switching logic waits until the clock that
is currently in use and the newly programmed clock
source are both low, and then switches from the
previous clock to the new clock without a glitch on
the clocks.
13 MHz
CLKEN
Figure 4. CLKEN Timing Entering the Standby State
EXPCLK
(internal)
RUN
CLKEN
Interrupt /
WAKEUP
26
Figure 5. CLKEN Timing Entering the Standby State
DS474PP1