EP7212 Datasheet, PDF (25/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
faces. In addition, when in the Standby State, the
LCD controller and PWM drive are also disabled.
When operating from an external 13 MHz oscilla-
tor which has become disabled in the Standby State
by using the CLKEN (SYSCON, bit 13) signal
(i.e., with CLKENSL = 0), the oscillator must be
stable within 0.125 sec from the rising edge of the
CLKEN signal.
3.5 Clocks
There are two clocking modes for the EP7212. Ei-
ther an external clock input can be used or the on-
chip PLL. The clock source is selected by a strap-
ping option on Port E, pin 2 (PE[2]). If PE[2] is
high at the rising edge of nPOR (i.e., upon power-
up), the external clock mode is selected. If PE[2] is
low, then the on-chip PLL mode is selected. After
power-up, PE[2] can be used as a GPIO.
The EP7212 device contains several separate sec-
tions of logic, each clocked according to its own
clock frequency requirements. When the EP7212 is
in external clock mode, the actual frequencies at
the peripherals will be different than when in PLL
mode. See each peripheral device section for more
details. The section below describes the clocking
for both the ARM720T and address/data bus.
3.5.1 On-Chip PLL
The ARM720T clock can be programmed to
18.432 MHz, 36.864 MHz, 49.152 MHz, or
73.728 MHz with the PLL running at twice the
highest possible CPU clock frequency
(147.456 MHz). The PLL uses an external
3.6864 MHz crystal. By chip default, the on-chip
PLL is used and configured such that the
ARM720T and address/data buses run at
18.432 MHz.
When the clock frequency is selected to be
36 MHz, both the ARM720T and the address/data
buses are clocked at 36 MHz. When the clock fre-
quency is selected higher than 36 MHz, only the
ARM720T gets clocked at this higher speed. The
address/data will be fixed at 36 MHz. The clock
frequency used is selected by programming the
CLKCTL[1:0] bits in the SYSCON3 register. The
clock frequency selection does not effect the EPB
(external peripheral bus). Therefore, all the periph-
eral clocks are fixed, regardless of the clock speed
selected for the ARM720T.
NOTE: After modifying the CLKCTL[1:0] bits, the
next instruction should always be a ‘NOP’.
3.5.1.1 Characteristics of the PLL Interface
When connecting a crystal to the on-chip PLL in-
terface pins (i.e. MOSCIN and MOSCOUT), the
crystal and circuit should conform to the following
requirements:
• The 3.6864 MHz frequency should be created
by the crystals fundamental tone (i.e., it should
be a fundamental mode crystal).
• A start-up resistor is not necessary, since one is
provided internally.
• Start-up loading capacitors may be placed on
each side of the external crystal and ground.
Their value should be in the range of 10 pF.
However, their values should be selected based
upon the crystal specifications. The total sum of
the capacitance of the traces between the
EP7212’s clock pins, the capacitors, and the
crystal leads should be subtracted from the
crystal’s specifications when determining the
values for the loading capacitors.
• The crystal should have a maximum 100 ppm
frequency drift over the chip’s operating tem-
perature range.
Alternatively, a digital clock source can be used to
drive the MOSCIN pin of the EP7212. With this
approach, the voltage levels of the clock source
should match that of the V_DD supply for the
EP7212’s pads (i.e. the supply voltage level used to
drive all of the non-V_DD core pins on the EP7212).
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