EP7212 Datasheet, PDF (90/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.16.2.2 DAIDR1 DAI Data Register 1
ADDRESS: 0x8000.2080
31:16
Reserved
31:16
Reserved
15:0
Bottom of Left Channel Receive FIFO
Read Access
15:0
Top of Left Channel Transmit FIFO
Write Access
When DAI Data Register 1 (DAIDR1) is read, the bottom entry of the Left Channel Receive FIFO is
accessed. As data is removed by the DAI’s receive logic from the incoming data frame, it is placed
into the top entry of the Left Channel Receive FIFO and is transferred down an entry at a time until it
reaches the last empty location within the FIFO. Data is removed by reading DAIDR1, which accesses
the bottom entry of the left channel FIFO. After DAIDR1 is read, the bottom entry is invalidated, and
all remaining values within the FIFO automatically transfer down one location.
When DAIDR1 is written, the top-most entry of the Left Channel Transmit FIFO is accessed. After a
write, data is automatically transferred down to the lowest location within the transmit FIFO which
does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time
by the transmit logic. It is then loaded into the correct position within the 64-bit transmit serial shifter
then serially shifted out onto the SDOUT pin.
Table 52 shows DAIDR1. Note that the Transmit and Receive Left Channel FIFOs are cleared when
the device is reset, or by writing a zero to DAIEN (DAI disabled). Also, note that writes to reserved
bits are ignored and reads return zeros.
Bit
0:15
16:31
Description
LEFT CHANNEL DATA: Transmit / Receive Left Channel FIFO Data
Read — Bottom of Left Channel Receive FIFO data
Write — Top of Left Channel Transmit FIFO data
Reserved
Table 52. DAI Data Register 1
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DS474PP1