EP7212 Datasheet, PDF (22/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
Address (W/B)
DRAM Control
UARTs
LCD FIFO
LCD
ADC Interface
SSI2 Interface
DAI Interface
Codec
Timers
RTC
LED Flasher
DC-to-DC
CPU
Interrupt Control
PLL/CLKEN Signal
Operating
Idle Standby
nPOR nURESET
RESET RESET
On
On SELFREF
Off
SELFREF
On
On
Off
Reset
Reset
On
On
Reset
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
Off
Reset
Reset
On
On
On
On
On
On
On
On
Reset
Reset
On
On
Off
Reset
Reset
On
Off
Off
Reset
Reset
On
On
On
Reset
Reset
On
On
Off
Off
Off
Table 7. Peripheral Status in Different Power Management States
Operating State to the Standby State. Before enter-
ing the Standby State, if external I/O devices (such
as the CL-PS6700s connected to nCS[4] or nCS[5])
are in use, the software must check to ensure that
they are idle before issuing the write to the Standby
State location.
Before entering the Standby State, the software
must properly disable the DAI. Failing to do so will
result in higher than expected power consumption
in the Standby State, as well as unpredictable oper-
ation of the DAI. The DAI can be re-enabled after
transitioning back to the Operating State.
The system can also be forced into the Standby
State by hardware if the nPWRFL or nURESET in-
puts are forced low. The only exit from the Standby
State is to the Operating State.
The system will only transition to the Operating
State from the Standby State under the following
conditions: when the nPWRFL input pin is high
when the nEXTPWR input pin is low or when the
BATOK input pin is high. This prevents the system
from starting when the power supply is inadequate
(i.e., the main batteries are low), corresponding to
a low level on nPWRFL or BATOK.
From the Standby State, if the WAKEUP signal is
applied with no clock except the 32 kHz clock run-
ning, the EP7212 will be initialized into a state
where it is ready to start and is waiting for the CPU
to start receiving its clock. The CPU will still be
held in reset at this point. After the first clock is ap-
plied, there will be a delay of about eight clock cy-
cles before the CPU is enabled. This delay is to
allow the clock to the CPU time to settle.
3.2.1.1 UART in Standby State
During the Standby State, the UARTs are disabled
and cannot detect any activity (i.e., start bit) on the
receiver. If this functionality is required then this
can be accomplished in software by the following
method:
1) Permanently connect the RX pin to one of the
active low external interrupt pins.
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