EP7212 Datasheet, PDF(27/136 Page) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212 Datasheet, PDF (27/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212

3.6 Interrupt Controller

When unexpected events arise during the execution

of a program (i.e., interrupt or memory fault) an ex-

ception is usually generated. When these excep-

tions occur at the same time, a fixed priority system

determines the order in which they are handled.

Table 8 shows the priority order of all the excep-

tions.

Priority

Highest

Lowest

Exception

Reset

Data Abort

FIQ

IRQ

Prefetch Abort

Undefined Instruction,

Software Interrupt

Table 8. Exception Priority Handling

The EP7212 interrupt controller has two interrupt

types: interrupt request (IRQ) and fast interrupt re-

quest (FIQ). The interrupt controller has the ability

to control interrupts from 22 different FIQ and IRQ

sources. Of these, seventeen are mapped to the IRQ

input and five sources are mapped to the FIQ input.

FIQs have a higher priority than IRQs. If two inter-

rupts are received from within the same group (IRQ

or FIQ), the order in which they are serviced must

be resolved in software. The priorities are listed in

Table 9. All interrupts are level sensitive; that is,

they must conform to the following sequence.

1) The interrupting device (either external or in-

ternal) asserts the appropriate interrupt.

2) If the appropriate bit is set in the interrupt mask

serted by the interrupt controller. (A descrip-

tion for each bit in this register can be found in

INTSR1 Interrupt Status Register 1).

3) If interrupts are enabled the processor will

jump to the appropriate address.

4) Interrupt dispatch software reads the interrupt

status register to establish the source(s) of the

interrupt and calls the appropriate interrupt ser-

vice routine(s).

5) Software in the interrupt service routine will

clear the interrupt source by some action spe-

cific to the device requesting the interrupt (i.e.,

reading the UART RX register).

The interrupt service routine may then re-enable in-

terrupts, and any other pending interrupts will be

serviced in a similar way. Alternately, it may return

to the interrupt dispatch code, which can check for

any more pending interrupts and dispatch them ac-

cordingly. The âEnd of Interruptâ type interrupts

are latched. All other interrupt sources (i.e., exter-

nal interrupt source) must be held active until its re-

spective service routine starts executing. See âEnd

Of Interrupt Locationsâ on page 83 for more de-

tails.

Table 9, Table 10, and Table 11 show the names

and allocation of interrupts in the EP7212.

3.6.1 Interrupt Latencies in Different

States

3.6.1.1 Operating State

The ARM720T processor checks for a low level on

its FIQ and IRQ inputs at the end of each instruc-

tion. The interrupt latency is therefore directly re-

lated to the amount of time it takes to complete

execution of the current instruction when the inter-

rupt condition is detected. First, there is a one to

two clock cycle synchronization penalty. For the

case where the EP7212 is operating at 13 MHz

with a 16-bit external memory system, and instruc-

tion sequence stored in one wait state FLASH

memory, the worst-case interrupt latency is

251 clock cycles. This includes a delay for cache

line fills for instruction prefetches, and a data abort

occurring at the end of the LDM instruction, and

the LDM being non-quad word aligned. In addi-

tion, the worst-case interrupt latency assumes that

LCD DMA cycles to support a panel size of 320 x

DS474PP1

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