EP7212 Datasheet, PDF (14/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
2.2 Pin Descriptions
Table 4 describes the function of all the external signals to the EP7212. Note that all output signals and all
I/O pins (when acting as outputs) are three stateable. This is to enable the Hi-Z test modes to be supported.
2.2.1 External Signal Functions
Function
Data bus
Address bus
Memory
Interface
Signal
Name
D[0-31]
A[0-14]
A[15-27]
DRA[0-12]
nRAS[0-1]
nCAS[0-3]
nMOE
nMWE
nCS[0-3]
nCS[4-5]
EXPRDY
WRITE
WORD/
HALFWORD
Signal
Description
I/O 32-bit system data bus for memory, DRAM, and I/O interface
O 15 bits of system byte address during memory and expansion cycles
DRA[0-12] is multiplexed with A[15-27], offering additional power savings
since the lightest loading is expected on the high order ROM address lines.
Whenever the EP7212 is in the Standby State, the external address and data
buses are driven low. The RUN signal is used internally to force these buses to
be driven low. This is done to prevent peripherals that are powered-down from
draining current. Also, the internal peripheral’s signals get set to their Reset
State.
O Row Address Select outputs to DRAM banks 0 to 1.
I/O Column Address Select outputs allowing for bytes 0 to 3 within a 32-bit word.
O Memory output enable
O Memory write enable
O Chip select; active low, SRAM-like chip selects for expansion
O Chip select; active low, CS for expansion or for CL-PS6700 select
I Expansion port ready; external expansion devices drive this low to extend the
bus cycle. This is used to insert wait states for an external bus cycle.
O Write strobe, low during reads, high during writes from the EP7212
O To do write accesses of different sizes Word and Half-Word must be externally
decoded. The encoding of these signals is as follows:
Access Size
Word
Half-Word
Byte
Word
1
*
0
Half-Word
0
1
0
EXPCLK
The core will generate an address. When doing a read, the ARM core will
select the appropriate byte channels. When doing a write, the correct bytes
will have to be enabled depending on the above signals and the least signifi-
cant bits of the address bus.
The ARM architecture does not support unaligned accesses. For a read using
x 32 memory, it is assumed that you will ignore bits 1 and 0 of the address bus
and perform a word read (or in power critical systems decode the relevant bits
depending on the size of the access). If an unaligned read takes place, the
core will rotate the resulting data in the register. For more information on this
behavior see the LDR instruction in the ARM7TDMI data sheet.
I/O Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It
runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is
used as the clock input.
Table 4. External Signal Functions
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