EP7212 Datasheet, PDF (103/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
DRAM Word Read followed by Page Mode Read (EXPCLK shown for reference only)
EXPCLK
DRA[12:0]
nRAS[1:0]
nCAS[3:0]
D[31:0]
ROW
COL
t_RAS
t_RC
t9
t_RP
ROW
t10
COL1 COL2 COLn
t11 ^t12
t_{CP tPC}
t_CAS
1
2
n
Figure 16. DRAM Read Cycles at 13 MHz and 18.432 MHz
NOTES: 1) t_RC (Read cycle time) = 150 ns max at 18.432 MHz and 230 ns at 13 MHz
2) t_RAS (RAS pulse width) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz
3) t_RP (RAS precharge time) = 70 ns max at 18.432 MHz and 110 ns at 13 MHz
4) t_CAS (CAS pulse width) = 20 ns max at 18.432 MHz and 30 ns at 13 MHz
5) t_CP (CAS precharge in page mode) = 12 ns max at 18.432 MHz and 20 ns at 13 MHz
6) t_PC (Page mode cycle time) = 45 ns min at max at 18.432 MHz and 70 ns at 13 MHz
Word reads shown, for byte reads, only one off nCAS[3:0] will be active, nCAS0 for byte 0, etc.
DS474PP1
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