EP7212 Datasheet, PDF (54/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5. REGISTER DESCRIPTIONS
5.1 Internal Registers
Table 27 shows the Internal Registers of the
EP7212 that are compatible with the CL-PS7111
when the CPU is configured to a little endian mem-
ory system. Table 28 shows the differences that oc-
cur when the CPU is configured to a big endian
memory system for byte-wide access to Ports A, B,
and D. All the internal registers are inherently little
endian (i.e., the least significant byte is attached to
bits 7 to 0 of the data bus). Hence, the system En-
dianness affects the addresses required for byte ac-
cesses to the internal registers, resulting in a
reversal of the byte address required to read / write
a particular byte within a register. Note that the in-
ternal registers have been split into two groups –
the “old” and the “new”. The old ones are the same
as that used in CL-PS7111 and are there for com-
patibility. The new registers are for accessing the
additional functionality of the DAI interface and
the LED flasher.
There is no effect on the register addresses for word
accesses. Bits A[0:1] of the internal address bus are
only decoded for Ports A, B, and D (to allow read /
write to individual ports). For all other registers,
bits A[0:1] are not decoded, so that byte reads will
return the whole register contents onto the
EP7212’s internal bus, from where the appropriate
byte (according to the endianness) will be read by
the CPU. To avoid the additional complexity, it is
preferable to perform all internal register accesses
as word operations, except for ports A to D which
are explicitly designed to operate with byte access-
es, as well as with word accesses.
An 8 k segment of memory in the range
0x8000.0000 to 0x8000.3FFF is reserved for inter-
nal use in the EP7212. Accesses in this range will
not cause any external bus activity unless debug
mode is enabled. Writes to bits that are not explic-
itly defined in the internal area are legal and will
have no effect. Reads from bits not explicitly de-
fined in the internal area are legal but will read un-
defined values. All the internal addresses should
only be accessed as 32-bit words and are always on
a word boundary, except for the PIO port registers,
which can be accessed as bytes. Address bits in the
range A[0:5] are not decoded (except for Ports
A–D), this means each internal register is valid for
64 bytes (i.e., the SYSFLG1 register appears at lo-
cations 0x8000.0140 to 0x8000.017C). There are
some gaps in the register map for backward com-
patibility reasons, but registers located next to a
gap are still only decoded for 64 bytes.
The GPIO port registers are byte-wide and can be
accessed as a word but not as a half-word. These
registers additionally decode A[0:1]. All addresses
are in hexadecimal notation.
NOTE:
All byte-wide registers should be accessed
as words (except Port A to Port D registers,
which are designed to work in both word and
byte modes).
All registers bit alignment starts from the
LSB of the register (i.e., they are all right shift
justified).
The registers which interact with the 32 kHz
clock or which could change during read-
back (i.e., RTC data registers, SYSFLG1
register (lower 6-bits only), the TC1D and
TC2D data registers, port registers, and
interrupt status registers), should be read
twice and compared to ensure that a stable
value has been read back.
All internal registers in the EP7212 are reset
(cleared to zero) by a system reset (i.e., nPOR,
nRESET, or nPWRFL signals becoming active),
and the Real Time Clock data register (RTCDR)
and match register (RTCMR), which are only reset
by nPOR becoming active. This ensures that the
system time preserved through a user reset or pow-
er fail condition. In the following register descrip-
tions, little endian is assumed.
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