EP7212 Datasheet, PDF(32/136 Page) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212 Datasheet, PDF (32/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212

not have an access time greater than 70 ns in order

to meet the 18 MHz timing requirements. When the

internal bus is operating at 36.864 MHz (i.e., for

CPU clock frequencies of 36.864, 49.152, or

73.728 MHz), the DRAM controller will only op-

erate with EDO DRAM. When operating at 36

MHz, the EDO DRAM must not have an access

time greater than 50 ns. The DRAM cycle timings

are adjusted to take advantage of the additional per-

formance available from fast EDO DRAM. In EDO

mode, the EP7212 design relies on the DRAM data

being driven to be available on the external data

bus during the entire high phase of the nCAS signal

so that it can be latched towards the end of the cy-

cle. In Fast Page mode, the data should be latched

at the rising edge of nCAS. It is not possible to use

the EP7212 with fast page mode DRAM at operat-

ing frequencies of 36 MHz or higher.

The DRAM controller breaks all sequential access,

so that the minimum page sizes defined can be sup-

ported. All of the possible page sizes are multiples

of the minimum page size, so by breaking up ac-

cesses on minimum page sizes by default, all ac-

cesses crossing larger page boundaries are broken

up.

Table 16 DRAM Address Mapping for a 32-Bit

DRAM Memory System shows the address map-

ping for various DRAMâs with square and non-

square row and address inputs. This assumes two

x16 devices are connected to each RAS line with

32-bit wide DRAM operation selected. This map-

ping is then repeated every 256 Mbytes for each

DRAM

Address

Pins

DRAM

Column x16

Mode

DRAM

Column x32

Mode

DRAM

Row x16

Mode

DRAM

Row x32

Mode

A11

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A17

A18

A20

A21

A19

A20

A22

A23

A21

A22

A24

A25

A23

A24

A26

A27

A25

A26

Table 15. Physical to DRAM Address Mapping

1. This bit will be generated by the DRAM controller.

7212 Pin Name

A[27]/DRA[0]

A[26]/DRA[1]

A[25]/DRA[2]

A[24]/DRA[3]

A[23]/DRA[4]

A[22]/DRA[5]

A[21]/DRA[6]

A[20]/DRA[7]

A[19]/DRA[8]

A[18]/DRA[9]

A[17]/DRA[10]

A[16]/DRA[11]

A[15]/DRA[12]

An example of the DRAM connections for a typical system can be found in Figure 12. A Maximum EP7212

Based System on page 52.

DS474PP1

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