EP7212 Datasheet, PDF (36/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
emulation because the DMA address generator
built into the EP7212 is dedicated to the LCD con-
troller interface. If DMA is enabled within the CL-
PS6700, it will assert its PDREQ signal to make a
DMA request. This can be connected to one of the
EP7212’s external interrupts and be used to inter-
rupt the CPU so that the software can service the
DMA request under program control.
Each of the CL-PS6700 devices can generate an in-
terrupt PIRQ. Since the PIRQ signal is an open
drain on the CL-PS6700 devices, two CL-PS6700
devices may be wired OR’ed to the same interrupt.
The circuit can then be connected to one of the
EP7212’s active low external interrupt sources. On
the receipt of an interrupt, the CPU can read the in-
terrupt status registers on the CL-PS6700 devices
to determine the cause of the interrupt.
All transactions are synchronized to the EXPCLK
output from the EP7212 in 18.432 MHz mode or
the external 13 MHz clock. The EXPCLK should
be permanently enabled, by setting the EXCKEN
bit in the SYSCON1 register, when the CL-PS6700
is used. The reason for this is that the PC Card in-
terface and CL-PS6700 internal write buffers need
to be clocked after the EP7212 has completed its
bus cycles.
A GPIO signal from the EP7212 can be connected
to the PSLEEP pin of the CL-PS6700 devices to al-
low them to be put into a power saving state before
the EP7212 enters the Standby State. It is essential
that the software monitor the appropriate status
registers within the CL-PS6700s to ensure that
there are no pending posted bus transactions before
the Standby State is entered. Failure to do this will
result in incomplete PC Card accesses.
3.11 Endianness
The EP7212 uses a little endian configuration for
internal registers. However, it is possible to con-
nect the device to a big endian external memory
system. The big-endian / little-endian bit in the
ARM720T control register sets whether the
EP7212 treats words in memory as being stored in
big endian or little endian format. Memory is
viewed as a linear collection of bytes numbered up-
wards from zero. Bytes 0 to 3 hold the first stored
word, bytes 4 to 7 the second, and so on. In the little
endian scheme, the lowest numbered byte in a word
is considered to be the least significant byte of the
word and the highest numbered byte is the most
significant. Byte 0 of the memory system should be
connected to data lines 7 through 0 (D[7:0]) in this
scheme. In the big endian scheme the most signifi-
cant byte of a word is stored at the lowest numbered
byte, and the least significant byte is stored at the
highest numbered byte. Therefore, byte 0 of the
memory system should be connected to data lines
31 through 24 (D[31:24]). Load and store are the
only instructions affected by the Endianness.
Tables 19 and 20 demonstrate the behavior of the
EP7212 in big and little endian mode, including the
effect of performing non-aligned word accesses.
The register definition section of this specification
defines the behavior of the internal EP7212 regis-
ters in the big endian mode in more detail. For fur-
ther information, refer to ARM Application Note
61, Big and Little Endian Byte Addressing.
3.12 Internal UARTs (Two) and SIR
Encoder
The EP7212 contains two built-in UARTs that of-
fers similar functionality to National Semiconduc-
tor’s 16C550A device. Both UARTs can support
bit rates of up to 115.2 kbits/s and include two 16-
byte FIFOs: one for receive and one for transmit.
One of the UARTs (UART1) supports the three
modem control input signals CTS, DSR, and DCD.
The additional RI input, and RTS and DTR output
modem control lines are not explicitly supported
but can be implemented using GPIO ports in the
EP7212. UART2 has only the RX and TX pins.
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