EP7212 Datasheet, PDF (109/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
EXPCLK
DRA[12:0]
NRAS[1:0]
NCAS[3:0]
D[31:0]
Held
t_CSA
t_RC
t_RAS
Row
Col
Held
Figure 23. DRAM CAS Before RAS Refresh Cycle at 36 MHz
NOTES: 1) t_CSA (CAS set-up time) = 8 ns max
2) t_RAS (RAS pulse width) = 60 ns max
3) t_RC (cycle time) = 167 ns max
When DRAMs are placed in self-refresh (entering the Standby State), the same timings, except that t_RAS
is extended indefinitely.
CL[2]
t20
t15
t16
CL[1]
t17
t18
t19
t21
FRM
t22
M
t23
DD[3:0]
NOTES:
1) The figure shows the end of a line.
2) If FRM is high during the CL[1] pulse, this marks the first line in the display.
3) CL[2] low time is doubled during the CL[1] high pulse
Figure 24. LCD Controller Timings
DS474PP1
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