EP7212 Datasheet, PDF (31/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
ROMs. For writable memory devices which use the
nMWE pin, zero wait state sequential accesses are
not permitted and one wait state is the minimum
which should be programmed in the sequential
field of the appropriate MEMCFG register. Bus cy-
cles can also be extended using the EXPRDY input
signal.
Page mode access is accomplished by setting
SQAEN = 1, which enables accesses of the form
one random address followed by three sequential
addresses, etc., while keeping nCS asserted. These
sequential bursts can be up to four words long be-
fore nCS is released to allow DMA and refreshes to
take place. This can significantly improve bus
bandwidth to devices such as ROMs which support
page mode. When SQAEN = 0, all accesses to
memory are by random access without nCS being
de-asserted between accesses. Again nCS is de-as-
serted after four consecutive accesses to allow
DMAS.
Bits 5 and 6 of the SYSCON2 register independent-
ly enable the interfaces to the CL-PS6700 (PC Card
slot drivers). When either of these interfaces are en-
abled, the corresponding chip select (nCS4 and/or
nCS5) becomes dedicated to that CL-PS6700 inter-
face. The state of SYSCON2 bit 5 determines the
function of chip select nCS4 (i.e., CL-PS6700 in-
terface or standard chip select functionality); bit 6
controls nCS5 in a similar way. There is no interac-
tion between these bits.
For applications that require a display buffer small-
er than 38,400 bytes, the on-chip SRAM can be
used as the frame buffer.
The width of the boot device can be chosen by se-
lecting values of PE[1] and PE[0] during power on
reset. The inputs in Table 14 are latched by the ris-
ing edge of nPOR to select the boot option.
3.9 DRAM Controller with EDO Support
The DRAM controller in the EP7212 provides all
the connections to directly interface to up to two
PE[1]
0
0
1
1
PE[0]
0
1
0
1
Boot Block
(nCS0)
32-bit
8-bit
16-bit
Undefined
Table 14. Boot Options
banks of (EDO) DRAM, and the width of the mem-
ory interface is programmable to 16-bits or 32-bits.
Both banks have to be of the same width. The
16/32-bit DRAM width selection is made based on
bit 2 of the SYSCON2 register. Each of the two
banks supported can be up to 256 Mbytes in size.
Two RAS lines and four CAS lines are provided,
with one CAS line per byte lane. The DRAM con-
troller does not support device size programmabil-
ity. Therefore, if two banks are implemented and
DRAM devices are used, a bank smaller than 256
Mbytes would be created leading to a segmented
memory map. Each segmented bank will be sepa-
rated by 256 Mbytes. Segments that are smaller
than the bank size will repeat within the bank. Ta-
ble 15. Physical to DRAM Address Mapping
shows the mapping of the physical address to
DRAM row and column addresses. This mapping
has been organized to support any DRAM device
size from 4 Mbits to 1 Gbits with a square row and
column configuration (i.e., the number of column
addresses is equal to the number of row addresses).
If a non-square DRAM is used, further fragmenta-
tion of the memory map will occur, however the
smallest contiguous segment will always be 1
Mbyte. With proper mapping of pages/sections by
the MMU, one can create contiguous memory
blocks.
On boot-up, the DRAM controller is configured for
operation with an 18.432 MHz internal bus speed,
and therefore, can support either fast page mode or
EDO DRAM. In this case, the read data from the
DRAM is latched within the EP7212 on the rising
edge of the nCAS output strobes. The DRAM must
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