EP7212 Datasheet, PDF(115/136 Page) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212 Datasheet, PDF (115/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212

Signal

TSEL *

XTLON *

PLLON *

PLLBP

RTCCLK

CLK1

OSC36

CLK576K

VREF

I/O

Function

PA5 PLL test mode

PA4 Enable to oscillator circuit

PA3 Enable to PLL circuit

PA0 Bypasses PLL

COL0 Output of RTC oscillator

COL1 1 Hz clock from RTC divider chain

COL2 36 MHz divided PLL main clock

COL4 576 KHz divided from above

COL6 Test clock output for PLL

Table 63. Oscillator and PLL Test Mode Signals

7.3 Debug / ICE Test Mode

This mode is selected by nTEST0 = 0, nTEST1 =

0, Latched nURESET = 1.

Selection of this mode enables the debug mode of

the ARM720T. By default, this is disabled which

saves approximately 3% on power.

7.4 Hi-Z (System) Test Mode

This mode selected by nTEST0 = 0, nTEST1 = 0,

Latched nURESET = 0.

This test mode asynchronously disables all output

buffers on the EP7212. This has the effect of re-

moving the EP7212 from the PCB so that other de-

vices on the PCB can be in-circuit tested. The

internal state of the EP7212 is not altered directly

by this test mode.

7.5 Software Selectable Test

Functionality

When bit 11 of the SYSCON register is set high, in-

ternal peripheral bus register accesses are output on

the main address and data buses as though they

were external accesses to the address space ad-

dressed by nCS[5]. Hence, nCS[5] takes on a dual

role, it will be active as the strobe for internal ac-

cesses and for any accesses to the standard address

range for nCS[5]. Additionally, in this mode, the

internal signals shown in Table 64 are multiplexed

out of the device on port pins.

Signal I/O Pin

Function

CLK

O PE0 Waited clock to CPU

nFIQ O PE1 nFIQ interrupt to CPU

nIRQ O PE2 nIRQ interrupt to CPU

Table 64. Software Selectable Test Functionality

This test is not intended to be used when LCD

DMA accesses are enabled. This is due to the fact

that it is possible to have internal peripheral bus ac-

tivity simultaneously with a DMA transfer. This

would cause bus contention to occur on the external

bus.

The âWaited clock to CPUâ is an internally ANDed

source that generates the actual CPU clock. Thus, it

is possible to know exactly when the CPU is being

clocked by viewing this pin. The signals nFIQ and

nIRQ are the two output signals from the internal

interrupt controller. They are input directly into the

ARM720T processor.

DS474PP1

115

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