EP7212 Datasheet, PDF (37/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
Address
(W/B)
Data in
Memory
(as seen
by the
EP7212)
Word + 0 (W) 11223344
Word + 1 (W) 11223344
Word + 2 (W) 11223344
Word + 3 (W) 11223344
Word + 0 (H) 11223344
Word + 1 (H) 11223344
Word + 2 (H) 11223344
Word + 3 (H) 11223344
Word + 0 (B) 11223344
Word + 1 (B) 11223344
Word + 2 (B) 11223344
Word + 3 (B) 11223344
Byte Lanes to Memory / Ports / Registers
Big Endian Memory
Little Endian Memory
7:0 15:8 23:16 31:24 7:0 15:8 23: 16 31: 24
R0 Contents
Big
Endian
Little
Endian
44 33 22
44 33 22
44 33 22
44 33 22
44 33 22
44 33 22
44 33 22
44 33 22
dc dc
dc
dc dc 22
dc 33 dc
44 dc
dc
11 44 33 22
11 44 33 22
11 44 33 22
11 44 33 22
11 44 33 22
11 44 33 22
11 44 33 22
11 44 33 22
11 44 dc dc
dc dc 33 dc
dc dc dc 22
dc dc dc dc
11 11223344 11223344
11 44112233 44112233
11 33441122 33441122
11 22334411 22334411
11 00001122 00003344
11 22000011 44000033
11 00003344 00001122
11 44000033 22000011
dc 00000011 00000044
dc 00000022 00000033
dc 00000033 00000022
11 00000044 00000011
NOTE: dc = don’t care
Table 19. Effect of Endianness on Read Operations
Address
(W/B)
Word + 0 (W)
Word + 1 (W)
Word + 2 (W)
Word + 3 (W)
Word + 0 (H)
Word + 1 (H)
Word + 2 (H)
Word + 3 (H)
Word + 0 (B)
Word + 1 (B)
Word + 2 (B)
Word + 3 (B)
Register
Contents
11223344
11223344
11223344
11223344
11223344
11223344
11223344
11223344
11223344
11223344
11223344
11223344
Byte Lanes to Memory / Ports / Registers
Big Endian Memory
Little Endian Memory
7:0 15:8
23:16
31:24 7:0 15:8 23:16 31:24
44 33
22
11
44 33
22
11
44 33
22
11
44 33
22
11
44 33
22
11
44 33
22
11
44 33
22
11
44 33
22
11
44 33
44
33
44 33
44
33
44 33
44
33
44 33
44
33
44 33
44
33
44 33
44
33
44 33
44
33
44 33
44
33
44 44
44
44
44 44
44
44
44 44
44
44
44 44
44
44
44 44
44
44
44 44
44
44
44 44
44
44
44 44
44
44
NOTE:
Bold indicates active byte lane.
Table 20. Effect of Endianness on Write Operations
DS474PP1
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