EP7212 Datasheet, PDF (86/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.16.1 DAIR DAI Control Register
ADDRESS: 0x8000.2000
31:24
Reserved
23
LBM
22
RCRM
21
RCTM
20
LCRM
19
LCTM
18
Reserved
17
ECS
16
DAIEN
15:0
Reserved
The DAI control register (DAIR) contains eight different bit fields that control various functions within
the DAI interface.
Bit
0:15
7
15
16
17
18
19
20
21
22
23
24:31
Description
Reserved
Must be set to 0x0404
Reserved
Reserved
DAIEN: DAI Interface Enable
0 — DAI operation disabled, control of the SDIN, SDOUT, SCLKLRCK, and LRCK pins given to
the SSI2 / codec / DAI pin mulitiplexing logic to assign I/O pins 60-64 to another block.
1 — DAI operation enabled
Note that by default, the SSI / CODEC have precedence over the DAI interface in regard to the
use of the I/O pins. Nevertheless, when bit 3 (DAISEL) of register SYSCON3 is set to 1, then the
above mentioned DAI ports are connected to I/O pins 60–64.
ECS: External Clock Select selects external MCLK when = 1.
Reserved
Must be 0.
LCTM: Left Channel Transmit FIFO Interrupt Mask
0 — Left Channel Transmit FIFO half-full or less condition does not generate an interrupt (LCTS
bit ignored).
1 — Left Channel Transmit FIFO half-full or less condition generates an interrupt (state of LCTS
sent to interrupt controller).
LCRM: Left Channel Receive FIFO Interrupt Mask
0 — Left Channel Receive FIFO half-full or more condition does not generate an interrupt (LCRS
bit ignored).
1 — Left Channel Receive FIFO half-full or more condition generates an interrupt (state of LCRS
sent to interrupt controller).
RCTM: Right Channel Transmit FIFO Interrupt Mask
0 — Right Channel Transmit FIFO half-full or less condition does not generate an interrupt
(RCTS bit ignored).
1 — Right Channel Transmit FIFO half-full or less condition generates an interrupt (state of
RCTS sent to interrupt controller).
RCRM: Right Channel Receive FIFO Interrupt Mask
0 — Right Channel Receive FIFO half-full or more condition does not generate an interrupt
(RCRS bit ignored).
1 — Right Channel Receive FIFO half-full or more condition generates an interrupt (state of
RCRS sent to interrupt controller).
LBM: Loopback Mode
0 — Normal serial port operation enabled
1 — Output of serial shifter is connected to input of serial shifter internally and control of SDIN,
SDOUT, SCLK, and LRCK pins is given to the PPC unit.
Reserved
Table 50. DAI Control Register
86
DS474PP1