EP7212 Datasheet, PDF (65/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
Bit
16:21
22
23
24
25
26
27:28
29
30:31
Description
RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last incre-
ment of the RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down
to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output.
URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the RX holding register is empty. If the FIFO is enabled, the URXFE bit will be set when the
RX FIFO is empty.
UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFI-
FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set
when the TX holding register is full. If the FIFO is enabled, the UTXFF bit will be set when the TX
FIFO is full.
CRXFE: Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty.
CTXFF: Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full.
SSIBUSY: Synchronous serial interface busy bit. This bit will be set while data is being shifted in
or out of the synchronous serial interface, when clear data is valid to read.
BOOTBIT0–1: These bits indicate the default (power-on reset) bus width of the ROM interface.
See Memory Configuration Registers for more details on the ROM interface bus width. The state
of these bits reflect the state of Port E[0:1] during power on reset, as shown in the table below.
PE[1]
(BOOTBIT1)
0
0
1
1
PE[0]
(BOOTBIT0)
0
1
0
1
Boot option
32-bit
8-bit
16-bit
Reserved
ID: Will always read ‘1’ for the EP7212 device.
VERID: Version ID bits. These 2 bits determine the version id for the EP7212. Will read ‘10’ for
the initial version.
Table 32. SYSFLG (cont.)
DS474PP1
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