EP7212 Datasheet, PDF (42/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
side of an audio sample. When LRCK transitions
from low to high the next 16-bits make up the right
side of an audio sample.
3.13.2.3 DAI Signals
MCLK
SCLK
LRCK
SDOUT
oversampled clock. Used as an in-
put to the EP7212 for generating the
DAI timing. This signal is also usu-
ally used as an input to a DAC/ADC
as an oversampled clock. This sig-
nal is fixed at 256 times the audio
sample frequency.
bit clock. Used as the bit clock input
into the DAC/ADC. This signal is
fixed at 128 times the audio sample
frequency.
Frame sync. Used as a frame syn-
chronization input to the
DAC/ADC. This signal is fixed at
the audio sample frequency. This
signal is clocked out on the negative
going edge of SCLK.
Digital audio data out. Used for
sending playback data to a DAC.
This signal is clocked out on the
negative going edge of the SCLK
output.
SDIN
Digital audio input. Used for receiv-
ing record data from an ADC. This
signal is latched by the EP7212 on
the positive going edge of SCLK.
3.13.3 ADC Interface — Master Mode Only
SSI1 (Synchronous Serial Interface)
The first synchronous serial interface allows inter-
facing to the following peripheral devices:
• In the default mode, the device is compatible
with the MAXIM MAX148/9 in external clock
mode. Similar SPI- or Microwire-compatible
devices can be connected directly to the
EP7212.
• In the extended mode and with negative-edge
triggering selected (the ADCCON and ADC-
CKNSEN bits are set, respectively, in the
SYSCON3 register), this device can be inter-
faced to Analog Devices’ AD7811/12 chip us-
ing nADCCS as a common RFS/TFS line.
• Other features of the devices, including power
management, can be utilized by software and
the use of the GPIO pins.
The clock output frequency is programmable and
only active during data transmissions to save pow-
er. There are four output frequencies selectable,
which will be slightly different depending whether
LRCK
SCLK
SDATA O
SDATAI
Left Channel
128 SCLKs
Right Channel
MSB _{-1 -2 -3 -4 -5 +5 +4 +3 +2 +1} LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
MSB _{-1 -2 -3 -4 -5 +5 +4 +3 +2 +1} LSB
MSB _{-1 -2 -3 -4 +5 +4 +3 +2 +1} LSB
Figure 8. EP7212 Rev C - Digital Audio Interface Timing – MSB / Left Justified format
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