EP7212 Datasheet, PDF (82/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.11 SSI Register
5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register
ADDRESS: 0x8000.0500
31:15
Reserved
In the default mode, the bits in SYNCIO have the following meaning:
14
13
12:8
7:0
TXFRMEN
SMCKEN
Frame length
ADC Configuration Byte
15
Reserved
Whereas in extended mode, the following applies:
14
13
12:7
TXFRMEN
SMCKEN
Frame length
6:0
ADC Configuration Length
ADC Configuration Extension
NOTE: The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read bits
(= 33 cycles).
SYNCIO is a 32-bit read / write register. The data written to the SYNCIO register configures the mas-
ter only SSI. In default mode, the least significant byte is serialized and transmitted out of the synchro-
nous serial interface1 (i.e., SSI1) to configure an external ADC, MSB first. In extended mode, a
variable number of bits are sent from SYNCIO[16:31] as determined by the ADC Configuration
Length. The transfer clock will automatically be started at the programmed frequency and a synchro-
nization pulse will be issued. The ADCIN pin is sampled on every positive going clock edge (or the
falling clock edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to the SYNCIO read
register.
During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will be
asserted. To clear the interrupt the SYNCIO register must be read. The data read from the SYNCIO
register is the last sixteen bits shifted out of the ADC.
The length of the data frame can be programmed by writing to the SYNCIO register. This allows many
different ADCs to be accommodated. The device is SPI- / Microwire-compatible (transfers are in mul-
tiples of 8 bits). However, to be compatible with some non-SPI / Microwire devices, the data written
to the ADC device can be anything between 8 to 16 bits. This is user-definable per the ADC Config-
uration Extension section of the SYNCIO register.
Bit
0:7 or 0:6
8:12 or 7:12
Description
ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is
the 8-bit configuration data to be sent to the ADC. When the ADCCON control bit in the
SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the
ADC Configuration Extension field for sending to the ADC.
Frame length: The Frame Length field is the total number of shift clocks required to complete a
data transfer.
In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit
+ 16 bits result).
In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).
Table 49. SYNCIO
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