EP7212 Datasheet, PDF (43/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
the device is operating in a 13 MHz mode or a
18.432 MHz–73.728 MHz mode (see Table 23).
The required frequency is selected by program-
ming the corresponding bits 16 and 17 in the
SYSCON1 register. The sample clock (SMPCLK)
always runs at twice the frequency of the shift
clock (ADCCLK). The output channel is fed by an
8-bit shift register when the ADCCON bit of
SYSCON3 is clear. When ADCCON is set, up to
16 bits of configuration command can be sent, as
specified in the SYNCIO register. The input chan-
nel is captured by a 16-bit shift register. The clock
and synchronization pulses are activated by a write
to the output shift register. During transfers the
SSIBUSY (synchronous serial interface busy) bit
in the system status flags register is set. When the
transfer is complete and valid data is in the 16-bit
read shift register, the SSEOTI interrupt is asserted
and the SSIBUSY bit is cleared.
An additional sample clock (SMPCLK) can be en-
abled independently and is set at twice the transfer
clock frequency.
This interface has no local buffering capability and
is only intended to be used with low bandwidth in-
terfaces, such as for a touch-screen ADC interface.
3.13.4 Master / Slave SSI2 (Synchronous
Serial Interface 2)
A second SPI / Microwire interface with full master
/ slave capability is provided by the EP7212. Data
rates in slave mode are theoretically up to
512 kbits/s, full duplex, although continuous oper-
ation at this data rate will give an interrupt rate of
2 kHz, which is too fast for many operating sys-
tems. This would require a worst-case interrupt re-
sponse time of less than 0.5 msec and would cause
loss of data through TX underruns and RX over-
runs.
The interface is fully capable of being clocked at
512 kHz when in slave mode. However, it is antic-
ipated that external hardware will be used to frame
the data into packets. Therefore, although the data
would be transmitted at a rate of 512 kbits/s, the
sustained data rate would in fact only be
85.3 kbits/s (i.e., 1 byte every 750 µsec). At this
data rate, the required interrupt rate will be greater
than 1 msec, which is acceptable.
There are separate half-word-wide RX and TX
FIFOs (16 half-words each) and corresponding in-
terrupts which are generated when the FIFO’s are
half-full or half-empty as appropriate. The inter-
SYSCON1
bit 17
0
0
1
1
SYSCON1
bit 16
0
1
0
1
13.0 MHz Operation ADCCLK
Frequency (kHz)
4.2
16.9
67.7
135.4
18.432–73.728 MHz Operation
ADCCLK Frequency (kHz)
4
16
64
128
Table 23. ADC Interface Operation Frequencies
DS474PP1
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