EP7212 Datasheet, PDF (7/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

EP7212
5.5 Timer / Counter Registers ................................................................................................. 74
5.5.1 TC1D Timer Counter 1 Data Register ..................................................................... 74
5.5.2 TC2D Timer Counter 2 Data Register ..................................................................... 74
5.5.3 RTCDR Real Time Clock Data Register ................................................................. 74
5.5.4 RTCMR Real Time Clock Match Register ............................................................... 74
5.6 LEDFLSH Register ........................................................................................................... 75
5.7 PMPCON Pump Control Register ..................................................................................... 76
5.8 CODR — The CODEC Interface Data Register ................................................................ 77
5.9 UART Registers ................................................................................................................ 77
5.9.1 UARTDR1–2, UART1–2 Data Registers ................................................................. 77
5.9.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers ................................. 78
5.10 LCD Registers ................................................................................................................. 79
5.10.1 LCDCON — The LCD Control Register ................................................................ 79
5.10.2 PALLSW Least Significant Word — LCD Palette Register ................................... 80
5.10.3 PALMSW Most Significant Word — LCD Palette Register ................................... 81
5.10.4 FBADDR LCD Frame Buffer Start Address ........................................................... 81
5.11 SSI Register .................................................................................................................... 82
5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register .................................. 82
5.12 STFCLR Clear all ‘Start Up Reason’ flags location ......................................................... 83
5.13 End Of Interrupt Locations .............................................................................................. 83
5.13.1 BLEOI Battery Low End of Interrupt ...................................................................... 83
5.13.2 MCEOI Media Changed End of Interrupt .............................................................. 83
5.13.3 TEOI Tick End of Interrupt Location ...................................................................... 83
5.13.4 TC1EOI TC1 End of Interrupt Location ................................................................. 83
5.13.5 TC2EOI TC2 End of Interrupt Location ................................................................. 84
5.13.6 RTCEOI RTC Match End of Interrupt .................................................................... 84
5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt .................................. 84
5.13.8 COEOI Codec End of Interrupt Location ............................................................... 84
5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................ 84
5.13.10 SRXEOF End of Interrupt Location ..................................................................... 84
5.14 State Control Registers ................................................................................................... 84
5.14.1 STDBY Enter the Standby State Location ............................................................. 84
5.14.2 HALT Enter the Idle State Location ....................................................................... 84
5.15 SS2 Registers ................................................................................................................. 85
5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ......................................... 85
5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte ............................... 85
5.16 DAI Register Definitions .................................................................................................. 85
5.16.1 DAIR DAI Control Register .................................................................................... 86
5.16.1.1 DAI Enable (DAIEN) .................................................................................. 87
5.16.1.2 DAI Interrupt Generation ........................................................................... 87
5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM) ................................. 87
5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM) ................................. 87
5.16.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM) .............................. 87
5.16.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) .............................. 88
5.16.1.7 Loopback Mode (LBM) .............................................................................. 88
5.16.2 DAI Data Registers ................................................................................................ 89
5.16.2.1 DAIDR0 DAI Data Register 0 .................................................................... 89
5.16.2.2 DAIDR1 DAI Data Register 1 .................................................................... 90
5.16.2.3 DAIDR2 DAI Data Register 2 .................................................................... 91
5.16.3 DAISR DAI Status Register ................................................................................... 92
5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS) ................... 94
5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS) ................... 94
5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS) ...................... 94
DS474PP1
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