EP7212 Datasheet, PDF(15/136 Page) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212 Datasheet, PDF (15/136 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)

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EP7212

Function

Interrupts

Power

Management

State Control

Signal

Name

nMEDCHG/

nBROM

nEXTFIQ

EINT[3]

nEINT[1:2]

nPWRFL1

BATOK1

nEXTPWR

nBATCHG1

nPOR

Signal

Description

I Media changed input; active low, deglitched. Used as a general purpose FIQ

interrupt during normal operation. It is also used on power up to configure the

processor to either boot from the internal Boot ROM, or from external memory.

When low, the chip will boot from the internal Boot ROM.

I External active low fast interrupt request input

I External active high interrupt request input

I Two general purpose, active low interrupt inputs

I Power fail input; active low, deglitched input to force system into the Standby

State

I Main battery OK input; falling edge generates a FIQ, a low level in the Standby

State inhibits system start up; deglitched input

I External power sense; must be driven low if the system is powered by an

external source

I New battery sense; driven low if battery voltage falls below the "no-battery"

threshold; it is a deglitched input

I Power-on reset input. This signal is not deglitched. When active it completely

resets the entire system, including all the RTC registers. Upon power-up, the

signal must be held active low for a minimum of 100 Âµsec after VDD has set-

tled. During normal operation, nPOR needs to be held low for at least one

clock cycle of the selected clock speed (i.e., when running at 13 MHz, the

pulse width of nPOR needs to be > 77 nsec).

RUN/CLKEN

WAKEUP1

nURESET1

Note that nURESET, RUN/CLKEN, TEST(0), TEST(1), PE(0), PE(1), PE(2),

DRIVE(0), DRIVE(1), DD(0), DD(1), DD(2), and DD(3) are all latched on the

rising edge of nPOR.

I/O This pin is programmed to either output the RUN signal or the CLKEN signal.

The CLKENSL bit is used to configure this pin. When RUN is selected, the pin

will be high when the system is active or idle, low while in the Standby State.

When CLKEN is selected, the pin will only be driven low when in the Standby

State (For RUN, see Table 6).

I Wake up is a deglitched input signal. It must also be held high for at

least 125 Âµsec to guarantee its detection. Once detected it forces the

system into the Operating State from the Standby State. It is only

active when the system is in the Standby State. This pin is ignored

when the system is in the Idle or Operating State. It is used to wakeup

the system after first power-up, or after software has forced the system

into the Standby State. WAKEUP will be ignored for up to two seconds

after nPOR goes HIGH. Therefore, the external WAKEUP logic must

be designed to allow it to rise and stay HIGH for at least 125 usec, two

seconds after nPOR goes HIGH.

I User reset input; active low deglitched input from user reset button.

This pin is also latched upon the rising edge of nPOR and read along with the

input pins nTEST[0-1] to force the device into special test modes. nURESET

does not reset the RTC.

Table 4. External Signal Functions (cont.)

DS474PP1

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