AK7735EQ Datasheet, PDF (94/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ Analog Input Block
1. Microphone Input Gain
The AK7735 has gain amplifiers for microphone input. The gain of L and R channels can be
independently selected by MGNL[3:0] and MGNR[3:0] bits (Table 45). The input impedance is typ. 20k
when ADC1VL/R bits is “0” and it is typ.25 k when ADC1VL/R bits are “1”. This gain amplifier executes
zero crossing detection when changing the gain by setting MICLZCE bit = “1” / MICRZCE bit = “1”. Zero
crossing detection is executed independently for L and R channels. Zero crossing timeout period is
16ms (@fs=48kHz base). When MICLZCE bit = “0”/ MICRZCE bit = “0”, the volume is changed
immediately by register settings.
When writing to MGNL/R[3:0] bits continuously, take an interval of zero crossing timeout period or more.
If the MGNL/R[3:0] bits are changed before zero crossing, the volume of Lch and Rch may differ. When
the volume level that is same as the present volume is set, the zero crossing counter is not reset and
time outs according to the previous writing timing. Therefore, in this case, writing to MGNL/R [3:0] bits
continuously is possible with a shorter interval of the zero crossing timeout period.
1-1. Microphone Gain
Mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MGNL[3]
MGNR[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MGNL[2] MGNL[1]
MGNR[2] MGNR[1]
MGNL[0]
MGNR[0]
Input Gain
0
0
0
0dB
0
0
1
2dB
0
1
0
4dB
0
1
1
6dB
1
0
0
8dB
1
0
1
10dB
1
1
0
12dB
1
1
1
14dB
0
0
0
16dB
0
0
1
18dB
0
1
0
21dB
0
1
1
24dB
1
0
0
27dB
1
0
1
30dB
1
1
0
33dB
1
1
1
36dB
Table 45. Microphone Input Gain
(default)
1-2. Zero Crossing Timeout
The microphone gain is changed independently on the timing of zero crossing detection or zero crossing
timeout.
48kHz base 44.1kHz base
Zero Crossing Timeout Period
16ms
17.4ms
Table 46. Zero Crossing Timeout Period
016014707-E-00
- 94 -
2016/12