AK7735EQ Datasheet, PDF (83/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
DxRESETN bit= “1”
(x=1,2)
CSN
SCLK
SI
don’t care
(L/H)
Command
don’t care
(L/H)
CRAM: 24H/26H, OFREG: 25H/27H
SO
Hi-Z
Address DATA DATA DATA DATA DATA
Hi-Z
RDY= “H”
Figure 58. CRAM/OFREG Write Preparation Data Read (SPI)
DxRESETN bit= “1”
(x=1,2)
CSN
SCLK
SI
RDY
don’tcare
(L/H)
Command
00000000
CRAM: A4H/A5H, OFREG: A2H/A3H
00000000
max 400ns
RDYLG * 67
Figure 59. CRAM/OFREG Write (SPI)
Notes
* 67. The RDY pin rises to “H” in two LRCK cycles at maximum if the DSP program is designed to access
the modification address in every sampling cycle. The RDY signal keeps “L” level even if a write
command is completed internally while CSN is “L” level.
* 68. Writing to a CRAM or OFREG address that is not used in the DSP program is prohibited during
RUN. If it is executed, the RDY pin keeps “L” output until the PDN pin becomes “L”. In the case of
I²C interface mode, communication will not be made correctly after that.
016014707-E-00
- 83 -
2016/12