AK7735EQ Datasheet, PDF (38/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
12. Functional Descriptions
■ System Clock
1. PLL Mode
The AK7735 has a PLL circuit to generate an internal operation clock. An input pin for the PLL reference
clock is selected by REFSEL[1:0] bits. REFMODE[4:0] bits set the frequency of the reference clock. A
reference clock input pin and the reference clock frequency must be changed during clock reset
(CKRESETN bit = “0”).
Mode
0
1
2
3
REFSEL[1:0] bits
Reference Clock Input Pin
Use of Crystal
Oscillator
00
XTI
Available
01
BICK1
N/A
10
BICK2
N/A
11
BICK3
N/A
Table 4. PLL Reference Clock Input Pin Select
(default)
Mode
REFMODE[4:0] bits
Input Frequency
48kHz base 44.1kHz base
0
00000
256kHz
235.2kHz (default)
1
00001
384kHz
352.8kHz
2
00010
512kHz
470.4kHz
3
00011
768kHz
705.6kHz
4
00100
1.024MHz
940.8kHz
5
00101
1.152MHz 1.0584MHz
6
00110
1.536MHz 1.4112MHz
7
00111
2.048MHz 1.8816MHz
8
01000
2.304MHz 2.1168MHz
9
01001
3.072MHz 2.8224MHz
10
01010
4.096MHz 3.7632MHz
11
01011
4.608MHz 4.2336MHz
12
01100
6.144MHz 5.6448MHz
13
01101
8.192MHz 7.5264MHz
14
01110
9.216MHz 8.4672MHz
15
01111
12.288MHz 11.2896MHz (X’tal available)
16
10000
18.432MHz 16.9344MHz (X’tal available)
17
10001
24.576MHz 22.5792MHz
Others
N/A
N/A
N/A
Table 5. PLL Reference Clock Frequency Setting (N/A: Not Available)
The PLL block multiplies an input clock which is set by REFMODE[4:0] bits directly and generates a
147.456MHz/135.4752MHz master clock (PLLMCLK) for internal operation.
Master Clock
48kHz base
44.1kHz base
(PLLMCLK)
147.456MHz
135.4752MHz
Table 6. Internal Operation Master Clock
016014707-E-00
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2016/12