AK7735EQ Datasheet, PDF (6/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ DSP Block Diagram
Pointer CP0, CP1
DP0, DP1
Coefficient RAM
6144×24Bit max
2048w Unit
Data RAM
4096w x 28Bit max
2048w Unit
CBUS(24Bit)
DBUS(28Bit)
DLP0, DLP1
OFREG
64w x 14Bit
Delay RAM
12288w x 28Bit max
4096w Unit
MPX24
MPX24
X
Y
Multiply
24×24 → 48Bit
48Bit
28Bit
52Bit
MUL DBUS
SHIFT
48Bit
A
B
ALU
52Bit
Overflow Margin: 4Bit
52-Bit
DR0  3
52Bit
Over Flow Data
Generator
Division 2424→24 _{Peak Detector}
Micon I/F
Control
Serial I/F
DEC
Program RAM
4096w×36Bit max
2048w Unit
PC
Stack : 8 Level(max)
TMP 12×28Bit
PTMP(LIFO) 6×28Bit
2 x 24Bit DIN6
2 x 24Bit DIN5
2 x 24Bit DIN4
2 x 24Bit DIN3
2 x 24Bit DIN2
2 x 24Bit DIN1
2 x 32Bit DOUT6
2 x 32Bit DOUT5
2 x 32Bit DOUT4
2 x 32Bit DOUT3
2 x 32Bit DOUT2
2 x 32Bit DOUT1
28bit x fifo16 DTMP
(Connection between DSP1/2)
Figure 2. DSP Block Diagram
Note
* 1. Coefficient RAM, Data RAM, Delay RAM, Program RAM areas are shared by DSP1 and DSP2 and
the sizes are configurable by control registers.
016014707-E-00
-6-
2016/12