AK7735EQ Datasheet, PDF (40/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ Audio HUB
1. Audio HUB
Audio HUB provides simultaneous data transmitting and flexible path configuration for various audio
sources by setting sample rate converters, input/output ports that support TDM mode and registers.
Therefore the AK7735 is able to support various use cases of audio systems.
2. Definition of Clock Sync Domain
The AK7735 has four Clock Sync Domains (Figure 15). Reference clocks (LRCKSDx, BICKSDx, x=1~4)
are output according to each register settings. The internal audio data and input/output data of the
AK7735 must be synchronized with one of these four Clock Sync Domains.
When MSNx bit =“0”, clocks from input pins (LRCKx pin/BICKx pin) are selected as reference clock of
clock sync domain 1~3. When MSNx bit = “1”, internal dividing clocks (MLRCKx/MBICKx) are selected
as reference clock of clock sync domain 1~3. For clock sync domain 4, internal dividing clocks
(MBICK4/MLRCK4) are selected as reference clock (BICKSD4/LRCKSD4) (Table 7).
Clock Sync Domain MSNx bit Reference Clock
Sync Domain x
(x=1 ~ 3)
Sync Domain 4
MSNx = 0 Clocks from Input Pins (BICKx pin/LRCKx pin)
Internal Dividing Clocks (MBICKx/MLRCKx)
MSNx = 1
Reference clock is generated internally by CKSx[2:0],
BDVx[9:0] and SDVx[2:0] bits settings.
Internal Dividing Clocks (MBICK4/MLRCK4)
-
Reference clock is generated internally by CKS4[2:0],
BDV4[9:0] and SDV4[2:0] bits settings.
Table 7. Reference Clock of Clock Sync Domain
PLLMCLK
XTI pin
BICK1~3 pin
p
LRCK1(pin Input)
BICK1(pin Input)
CKS1[2:0]
DIV
BDV1[9:0]
MBICK1
DIV
SDV1[2:0]
MLRCK1
LRCK2(pin Input)
BICK2(pin Input)
CKS2[2:0] / BDV2[9:0] / SDV2[2:0]
LRCK3(pin Input)
BICK3(pin Input)
CKS3[2:0] / BDV3[9:0] / SDV3[2:0]
LRCKSD1
BICKSD1
MSN1
LRCKSD2
BICKSD2
MSN2
LRCKSD3
BICKSD3
MSN3
CKS4[2:0] / BDV4[9:0] / SDV4[2:0]
LRCKSD4
BICKSD4
Figure 15. Definition of Clock Sync Domain
016014707-E-00
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2016/12