AK7735EQ Datasheet, PDF (81/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
4. RAM and Register Write/Read Timing
4-1. RAM Write Timing during DSP Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP reset in
the order of command code (8 bits), address (16 bits) and data. When writing the data to consecutive
address locations, continue to input data only. Address is incremented by 1 automatically.
DxRESETN bit
(x=1,2)
CSN
SCLK
SI
don’t care
(L/H)
Command
Address
DATA DATA
DATA
DATA
DATA
don’t care
(L/H)
RDY = “H”
Figure 55. Writing to RAM at Consecutive Address Locations (SPI)
DxRESETN bit
(x=1,2)
CSN
SCLK
SI
don’tcare
(L/H)
Command Address DATA
don’tcare
(L/H)
Command Address DATA
don’tcare
(L/H)
RDY = “H”
Figure 56. Writing to RAM at Random Address Locations (SPI)
016014707-E-00
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2016/12