AK7735EQ Datasheet, PDF (45/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
6. Clock Sync Domain Setting of DSP
Clock sync domain of DSP1 is selected by SDDSP1[2:0] bits. The DSP1 input port inherits the sync
domain of the input data. Clock sync domain of the output ports are set by SDDSP1O1[2:0] ~
SDDSP1O6[2:0] bits.
Clock sync domain of DSP2 is selected by SDDSP2[2:0] bits. The DSP2 input port inherits the sync
domain of the input data. Clock sync domain of the output ports are set by SDDSP2O1[2:0] ~
SDDSP2O6[2:0] bits.
DSP’s Sync Domain Input Port Sync Domain
Output Port Sync Domain
DSP1 SDDSP1[2:0] bits
Inherit the Sync Domain of Input data
Set by SDDSP1O1[2:0] bits ~
SDDSP1O6[2:0] bits
DSP2 SDDSP2[2:0] bits
Inherit the Sync Domain of Input data
Set by SDDSP2O1[2:0] bits ~
SDDSP2O6[2:0] bits
Table 17. Sync Domain Setting of DSP
Note
* 52. The sync domains of Input/Output ports should synchronize with the sync domain of DSP.
016014707-E-00
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2016/12