AK7735EQ Datasheet, PDF (64/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ Power-up Sequence
The AK7735 should be powered up when the PDN pin = “L”. Set the PDN pin to “H” to start the power
supply circuits for REF (reference voltage source) generator and digital circuits after all power supplies
are fed. By setting the PDN pin to “H”, control registers are initialized. Control register settings should be
made with an interval of 1ms or more after the PDN pin = “H”.
The PLL starts operation by a clock reset release (CKRESETN bit = “0” → “1”) and generates the
internal master clock after setting control registers. Therefore, necessary system clock must be input
before a clock reset release.
Interfacing with the AK7735 except control register settings should be made when PLL oscillation is
stabilized after clock reset release (take a 10ms interval or confirm “H” output of PLLLOCK signal from
the STO bit (Figure 46)). However, DSP program and coefficient data can be written even when the
system clock is stopped or during clock reset (CKRESETN bit= “0”). DSP program and coefficient data
can be written in 1ms by setting DLRDY bit “0” → “1”. DLRDY bit must be set to “0” after downloading
programs or data ( Figure 47).
112H
When using a crystal oscillator, release clock reset after crystal oscillation is stabilized. The stabilizing
time of crystal oscillation is dependent on the crystal and external circuits.
The system clock must not be stopped except during clock reset and power-down mode (PDN pin = “L”).
Figure 46. Power-up Sequence
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2016/12