AK7735EQ Datasheet, PDF (92/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
BANK size and BANK addressing mode of DRAM, that is assigned, can be set independently for the
DSP1 and the DSP2.
DRAM BANK sizes for DSP1 and DSP2 are controlled by D1DRMBK[1:0] bits and D2DRMBK[1:0] bits,
respectively.
Mode
D1DRMBK[1:0] bits
D2DRMBK[1:0] bits
BANK 1 Size
BANK 0 Size
0
00
1024
Rest of Area
(default)
1
01
2048
Rest of Area
2
10
3072
Rest of Area
3
11
N/A
N/A
Table 39. DRAM BANK Size Setting for DSP1 and DSP2 (N/A: Not Available)
DRAM BANK addressing modes for DSP1 and DSP2 are controlled by D1DRMA[1:0] bits and
D2DRMA[1:0] bits, respectively.
Mode
D1DRMA[1:0] bits
D2DRMA[1:0] bits
BANK 1 (DP1)
BANK 0 (DP0)
0
00
Ring
Ring
(default)
1
01
Ring
Linear
2
10
Linear
Ring
3
11
Linear
Linear
Table 40. DRAM BANK Addressing Mode Setting for DSP1 and DSP2
BANK size and BANK addressing mode of DLRAM, that is assigned, can be set independently for the
DSP1 and DSP2.
DLRAM BANK sizes for DSP1 and DSP2 are controlled by D1DLRMBK[2:0] bits and D2DLRMBK[2:0]
bits, respectively.
Mode
D1DLRMBK [2:0] bits
D2DLRMBK [2:0] bits
BANK 1 Size
BANK 0 Size
0
000
0
Rest of Area
(default)
1
001
2048 word
Rest of Area
2
010
4096 word
Rest of Area
3
011
6144 word
Rest of Area
4
100
8192 word
Rest of Area
5
101
10240 word
Rest of Area
6
110
12288 word
0
7
111
N/A
N/A
Table 41. DLRAM BANK Size Setting for DSP1 and DSP2 (N/A: Not Available)
DLRAM BANK addressing modes for DSP1 and DSP2 are controlled by D1DLRMA bit and D2DLRMA
bit, respectively.
Mode
D1DLRMA bit
D2DLRMA bit
BANK 1
BANK 0
0
0
Ring
Ring
(default)
1
1
Linear
Ring
Table 42. DLRAM BANK Addressing Mode Setting for DSP1 and DSP2
016014707-E-00
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2016/12