AK7735EQ Datasheet, PDF (88/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
2. Write Sequence
In the AK7735, when a “Write-Slave-address assignment” is received at the first byte, the write
command at the second byte, the address at the third and fourth bytes, and data at the fifth and
succeeding bytes are received. The number of write data bytes is fixed by the received command code.
S
T
A
R
T
SDA S
R/W=”0”
Slave
Address
Command
Code
Address(0)
Address(1)
Data(0)
Data(1)
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 67. Write Sequence (I²C)
S
T
O
P
Data(n)
P
A
A
C
C
K
K
3. Read Sequence
In the AK7735, when a “write- slave-address assignment” is received at the first byte, the read command
at the second byte and the address at the third and fourth bytes are received. When the fourth byte is
received and an acknowledgement is transferred, the read command waits for the next restart condition.
When a “read slave-address assignment” is received at the first byte, data is transferred at the second
and succeeding bytes. The number of readable data bytes is fixed by the received read command.
After reading the last byte, assure that a “not acknowledged” signal is received. If this “not
acknowledged” signal is not received, the AK7735 continues to send data regardless whether data is
present or not, and since it did not release the BUS, the stop condition cannot be properly received.
S
T
A
R/W=”0”
R
T
SDA
S
Slave
Address
Command
Code
Address(0)
Address(1)
R
E
S
T
R/W=”1”
A
R
T
S
Slave
Address
Data(0)
A
A
A
A
A
C
C
C
C
C
K
K
K
K
K
Figure 68. Read Sequence (I²C)
Data(1)
MA
MA
AC
AC
SK
SK
T
T
E
E
R
R
S
T
O
P
Data(n)
P
MA
MN
AC
AA
SK
SC
T
TK
E
E
R
R
016014707-E-00
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2016/12