AK7735EQ Datasheet, PDF (51/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
Source Select
Registers
Contents
Output Port
Clock Sync Domain
Setting Register
SELDO1A[5:0]
SDOUT1(pin) Output
TDMO1 Slot1, Slot2
SELDO1B[5:0]
TDMO1 Slot3, Slot4
SDOUT1 SDDO1[2:0]
SELDO1C[5:0]
TDMO1 Slot5, Slot6
SELDO1D[5:0]
TDMO1 Slot7, Slot8
SELDO2A[5:0]
SDOUT2(pin) Output
TDMO2 Slot1, Slot2
SELDO2B[5:0]
TDMO2 Slot3, Slot4
SDOUT2 SDDO2[2:0]
SELDO2C[5:0]
TDMO2 Slot5, Slot6
SELDO2D[5:0]
TDMO2 Slot7, Slot8
SELDO3A[5:0]
SDOUT3(pin) Output
TDMO3 Slot1, Slot2
SELDO3B[5:0]
TDMO3 Slot3, Slot4
SDOUT3 SDDO3[2:0]
SELDO3C[5:0]
TDMO3 Slot5, Slot6
SELDO3D[5:0]
TDMO3 Slot7, Slot8
SELDO4A[5:0]
SDOUT4(pin) Output
TDMO4 Slot1, Slot2
SELDO4B[5:0]
TDMO4 Slot3, Slot4
SDOUT4 SDDO4[2:0]
SELDO4C[5:0]
TDMO4 Slot5, Slot6
SELDO4D[5:0]
TDMO4 Slot7, Slot8
SELDA1[5:0]
SELDA2[5:0]
DAC1 Input
DAC2 Input
DAC1
DAC2
SDCODEC[2:0]
D1SELDI1[5:0]
DSP1 Input 1
DIN101 (Auto)
D1SELDI2[5:0]
DSP1 Input 2
DIN102 (Auto)
D1SELDI3[5:0]
DSP1 Input 3
DIN103 (Auto)
D1SELDI4[5:0]
DSP1 Input 4
DIN104 (Auto)
D1SELDI5[5:0]
DSP1 Input 5
DIN105 (Auto)
D1SELDI6[5:0]
DSP1 Input 6
DIN106 (Auto)
D2SELDI1[5:0]
DSP2 Input 1
DIN201 (Auto)
D2SELDI2[5:0]
DSP2 Input 2
DIN202 (Auto)
D2SELDI3[5:0]
DSP2 Input 3
DIN203 (Auto)
D2SELDI4[5:0]
DSP2 Input 4
DIN204 (Auto)
D2SELDI5[5:0]
DSP2 Input 5
DIN205 (Auto)
D2SELDI6[5:0]
DSP2 Input 6
DIN206 (Auto)
SELSRCI1[5:0]
SRC1 Input
SRCI1 (Auto)
SELSRCI2[5:0]
SRC2 Input
SRCI2 (Auto)
Table 20. Source Select Registers of Output Ports
Notes
* 53. If the output port source is changed to ALL0 when the clock sync domain setting is “Auto”, the clock
sync domain before changing the data source will be kept. This clock sync domain should not be
stopped immediately after changing the data source otherwise the output data will not become
ALL0 correctly.
* 54. Clock Sync Domain of the SDINx pin is automatically selected by setting EXBCKx[1:0] bits, MSNx
bit and SDBCKx[2:0] bits (Table 14, Table 15, Table 16).
* 55. SDINxB~D are only valid in TDM mode. These ports are fixed to “0” if it is not in TDM mode.
* 56. Input data to the input port 1~6 of the DSP must be selected from a data based on a clock sync
domain which is synchronized with PLLMCLK.
016014707-E-00
- 51 -
2016/12