AK7735EQ Datasheet, PDF (91/142 Pages) Asahi Kasei Microsystems – Dual DSP with 4chADC + 4chDAC + 4chSRC

[AK7735]
■ DSP Block
1. Settings of DSP Memory
The AK7735 integrates two DSPs (DSP1 and DSP2) which have the same architecture. The DSP1 and
the DSP2 share program RAM (PRAM), coefficient RAM (CRAM) data RAM (DRAM) and delay RAM
(DLRAM). Assigned memory area for each DSP is set by register settings. Both DSPs must be in reset
state when setting memory assignment.
PRAMDIV bit controls PRAM assignment for DSP1 and DSP2. CRAMDIV[1:0] bits control CRAM
assignment, DRAMDIV bit controls DRAM assignment and DLRAMDIV[1:0] bits control DLRAM
assignment.
Mode
PRAMDIV bit
DSP1
DSP2
0
0
2048 word
2048 word
1
1
4096 word
Reset
Table 35. PRAM Assignment for DSP1 and DSP2
Note
* 75. The DSP2 must be reset when setting to Mode 1 (PRAMDIV bit = “1”).
(default)
Mode CRAMDIV[1:0] bits
DSP1
DSP2
0
00
1
01
2
10
3
11
4096 word
2048 word
6144 word
N/A
2048 word
4096 word
Reset
N/A
(default)
Table 36. CRAM Assignment for DSP1 and DSP2 (N/A: Not Available)
Note
* 76. The DSP2 must be reset when setting to Mode 2 (CRAMDIV[1:0] bits = “10”).
Mode
DRAMDIV bit
DSP1
DSP2
0
0
2048 word
2048 word
1
1
4096 word
Reset
Note
Table 37. DRAM Assignment for DSP1 and DSP2
* 77. The DSP2 must be reset when setting to Mode 1 (DRAMDIV bit = “1”).
(default)
Mode DLRAMDIV[1:0] bits
DSP1
DSP2
0
00
12288 word
Not Connected (default)
1
01
8192 word
4096 word
2
10
4096 word
8192 word
3
11
Not Connected
12288 word
Table 38. DLRAM Assignment for DSP1 and DSP2
Note
* 78. The DSP1 and DSP2 can be operated without connecting to DLRAM. However, program access to
DLRAM is not permitted.
016014707-E-00
- 91 -
2016/12